Age | Commit message (Collapse) | Author | Files | Lines |
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Add pinctrl config about usb/sdio0
Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
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Enable STARFIVE_PINCTRL and PINCTRL_FULL
Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
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Add pinctrl driver for StarFive JH7110 SoC.
Signed-off-by: Kuan Lim Lee <kuanlim.lee@linux.starfivetech.com>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
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Add pinctrl definitions for StarFive JH7110 SoC.
Signed-off-by: Kuan Lim Lee <kuanlim.lee@linux.starfivetech.com>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
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CR_2555: borad:jh7110:evb: Modify ramdisk_addr_r/pxefile_addr_r/scriptaddr
See merge request sdk/u-boot!17
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The jh7110 ddr starts from 0x40000000. Using 0x80000000 may cause the
CMA space to fail
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
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CR_2522: support gamc with jh7110B-evb
See merge request sdk/u-boot!16
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Switch the QSPI parent clock to pll0 to improve the QSPI speed
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
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JH7110B requires a higher IOPAD capability in 1000M mode.
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
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JH7110B need tx_inverted by YT8521 phy, you need to read the chip
version to determine whether to use it.
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
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Read the chip model from the rgpio3 and setenv "chip_vision"
1: jh7110B
0: JH7110A
defalut: JH7110A
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
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JH7110B needs switch gmac0/1 tx to rgmii phy.
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
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JH7110B requires tx_inverted_10/100/1000 configuration, and different
parameters
may be required in 10M/100M/1000M mode.
This parameter supports JH7110B+YT8531PHY by default. Other boards can
modify the parameters of the tx_inverted_10/100/1000 to obtain support.
If you do not configure tx_inverted_10/100/1000 in dts, the default is
0.
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
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support use original or inverted RGMII_TX_CLK delay train.
10M/100M/1000M can be configured independently.
tx_inverted_xx = val;
For example:
&gmac0 {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@0 {
tx_inverted_10 = <0>;
tx_inverted_100 = <1>;
tx_inverted_1000 = <1>;
};
};
0: original (default)
1: inverted
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
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This patch include four items:
1.rename the driver compatible name.
2.reset action with the common API.
3.clean up code to make it is closer to readable.
4.add configuration to support 8G size
Signed-off-by: Yan Hong Wang <yanhongwang@linux.starfivetech.com>
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Add reset property configuration to DDR control device tree node.
Signed-off-by: Yan Hong Wang <yanhongwang@linux.starfivetech.com>
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Replace the configuration operation for pll1 clk with common api provide
by pll module.
Signed-off-by: Yan Hong Wang <yanhong.wang@starfivetech.com>
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Modify the parameters pass to clk_register() for pll0/pll1/pll2 clk.
Signed-off-by: Yan Hong Wang <yanhong.wang@starfivetech.com>
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Switch the pll2 clk to 1188M with the comm pll interface on JH7110.
Signed-off-by: Yan Hong Wang <yanhong.wang@starfivetech.com>
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Add common interface to set and get pll clk information for jh7110 soc.
Signed-off-by: Yan Hong Wang <yanhong.wang@starfivetech.com>
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ARP_TIMEOUT is too large, then will waite a long time for the first time
Set ARP_TIMEOUT to 500 refer to others
Set PHY_ANEG_TIMEOUT needs longer aneg time for the 2nd phy
Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
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The previous definition of apb_bus clock relationship is incorrect,so
update it.
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
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Add saveenv config to Support saveenv
Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
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Signed-off-by: samin <samin.guo@starfivetech.com>
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Configure SD card boot parameters
Signed-off-by: Clivia.Cai <Clivia.Cai@starfivetech.com>
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Change Model to "StarFive JH7110 EVB", and change riscv,isa to
"rv64imafdcbsux"
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
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The ddr driver include two configs with 2G and 4G.Fist read the ddr size
config from the memory node in the dts,then match the right config and
do it.
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
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In the hardware design, the IPs RESET signal of jh7110 is divided into
two groups,one group is active high, and the other group is active low.
However, the software does not need to distinguish whether the RESET
signal is active high or active low,Write 1 to be assert, and write 0 to deassert.
Therefore, the software does not need to add additional logic to
distinguish these two sets of signals.
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
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pll0 dynamically gets the frequency.
Signed-off-by: samin <samin.guo@starfivetech.com>
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The cpu uses 1.25G by default.
Lists of frequencies(MHz):
-375/500/625/750/875/1000/1250
-1375/1500/1625/1750/1800
Note: Some frequencies require voltage regulation.
Signed-off-by: samin <samin.guo@starfivetech.com>
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replace them with spl_cpu_set_rate.
Signed-off-by: samin <samin.guo@starfivetech.com>
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Add SPL_DM_RESET to defconfig, and update uart3-uart5 reset for StarFive
JH7110 SoC.
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
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Update Kconfig to support reset in SPL for StarFive JH7110 SoC.
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
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Update uart3-uart5 clks register info for StarFive JH7110 SoC.
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
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Add a list of clk enable operation.
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
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Modify the default division factor of sdcard clk to 4.
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
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Add usb init config for starfive EVB board. Default set to USB2.0
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
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Remove pll0/pll1/pll2 clk define from jh7110_clk.dts to clk-jh7110.c
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
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Modify the tx delay configuration.
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
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High-speed emmc/sdio support
Signed-off-by: samin <samin.guo@starfivetech.com>
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The default GPIO domian0-3 voltage is 3.3V, which is controlled by 4
bits. 0 means 3.3.V, 1 means 1.8V.
Signed-off-by: samin <samin.guo@starfivetech.com>
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Modify the GPIO configuration for sd&emmc module, switch the clk of sd&emmc
to high frequency
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
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Modify SD&EMMC node configuration on Starfive EVB board.
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
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Adjust CPU working frequency from 1G to 1.25G for starfive EVB board.
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
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Add MICREL phy config to defconfig for starfive EVB board.
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
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Add two macaddress for gmac0 and gmac1. Enable prefetcher for EVB board.
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
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Add ethernet-phy delay_chain configuration for gmac1 on starfive EVB
board.
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
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Add JH7110_GMAC1_GTXC clk for GMAC1 on JH7110
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
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Phy-reset-gpio set is unused in JH7110
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
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Modify the dynamic alloc memory start address from L2 LIM to DDR.
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
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