summaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
2023-07-18dram: jh7110: remove resize-ddr functionSamin Guo1-40/+10
The resize-ddr should be board-level code Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2023-07-12Merge branch 'CR_5623_1GDDR_samin.guo' into 'jh7110-master'andy.hu7-52/+118
CR5623： Add 1G DDR support && Simplify the command of uboot to load Linux See merge request sdk/u-boot!57
2023-07-10borad: starfive: evb: Synchronize environment variables from vf2Samin Guo1-0/+4
loadaddr fdtoverlay_addr_r kernel_comp_addr_r/kernel_comp_size Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2023-07-10borad: starfive: evb: Resize the address spaceSamin Guo1-20/+8
Readjust the address space for 1G DDR Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2023-07-10riscv: jh7110: add spi nor flash SPI_FLASH_MACRONIX supportSamin Guo1-0/+1
Radxa uses macronix spi flash, so enable it. Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2023-07-10riscv: jh7110: set SPL_OPENSBI_LOAD_ADDRSamin Guo1-0/+1
set SPL_OPENSBI_LOAD_ADDR to 0x40000000 Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2023-07-10dram: starfive: jh7110: Add 1G supportSamin Guo5-29/+47
add 1G DDR tuning cfg Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2023-07-10dram: jh7110: Add CONFIG_ID_EEPROM to determine if EEPROM is availableSamin Guo1-18/+26
When eeprom reads, you need to determine whether eeprom supports it. Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2023-07-10dram: jh7110: Macro definitions STARFIVE_JH7110_EEPROM_DDRINFO_OFFSETSamin Guo1-1/+2
In order to read DDR info from eeprom. Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2023-06-25dram: jh7110: Add resize DDR info from EEPROM.Samin Guo1-2/+47
sync from vf2 and add resize DDR info from EEPROM Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2023-06-20Merge branch 'CR_6164_evb_uboot_mem_keith.zhao' into 'jh7110-master'andy.hu1-1/+1
CR 6164 riscv: config: starfive: jh7110: mem size See merge request sdk/u-boot!56
2023-06-20riscv: config: starfive: jh7110: mem sizeKeith Zhao1-1/+1
reduce the mem size from 800+M to 128M Signed-off-by: Keith Zhao <keith.zhao@starfivetech.com>
2023-06-07Merge branch 'CR_5469_CPU_Max_Speed_mason.huo' into 'jh7110-master'andy.hu2-41/+33
CR_5469 board: starfive: jh7110: Add support for 1.25GHz chips See merge request sdk/u-boot!55
2023-06-05board: starfive: jh7110: Add support for 1.25GHz chipsMason Huo2-41/+33
Remove max cpu voltages: 1.12v, 1.10v, 1.08v. Set the cpu max frequency to 1.25G per OTP value. Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
2023-05-19Merge branch 'CR_3508_update_toolchain' into 'jh7110-master'andy.hu1-6/+6
CR_3508: riscv: dts: starfive: add zicsr_zifencei to riscv,isa string See merge request sdk/u-boot!54
2023-05-18riscv: dts: starfive: add zicsr_zifencei to riscv,isa stringAndy Hu1-6/+6
Starting from gcc 12.x, csr and fence instructions have been separated from the base I instruction set. special the zicsr_zifencei string to DT riscv,isa string Signed-off-by: Andy Hu <andy.hu@starfivetech.com>
2023-05-10Merge branch 'CR_5042_gmac_phy_delay_ds_samin.guo' into 'jh7110-master'andy.hu1-2/+20
CR5042： net: phy: motorcomm: add Pad Drive Strength Cfg See merge request sdk/u-boot!52
2023-05-10Merge branch 'CR_4854_nvboot_shanlong.li' into 'jh7110-master'andy.hu2-1/+17
CR_4854: uboot: evb support boot from nvme ssd See merge request sdk/u-boot!53
2023-05-05uboot: evb support boot from nvme ssdshanlong.li2-1/+17
support boot from nvme ssd Signed-off-by: shanlong.li <shanlong.li@starfivetech.com>
2023-04-26Merge branch 'CR_5041_Copyright_yanhong.wang' into 'jh7110-master'andy.hu29-30/+31
CR 5041 board: starfive: copyright: Standardize the copyright format See merge request sdk/u-boot!51
2023-04-23board: starfive: copyright: Standardize the copyright formatYanhong Wang29-30/+31
Unify the content format of the copyright section Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
2023-04-20net: phy: motorcomm: add Pad Drive Strength CfgSamin Guo1-2/+20
YT8531 supports Pad Drive Strength configuration. Including rx_data/rx_clk, etc. Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2023-04-19Merge branch 'CR_4747_remove_cycles_pmu_dts_minda' into 'jh7110-master'andy.hu1-5/+2
CR_4747 dts: pmu: remove pmu dts stall cycles config. See merge request sdk/u-boot!50
2023-04-12Merge branch 'CR_4427_DEFCONFIG_yanhong.wang' into 'jh7110-master'andy.hu1-1/+2
CR 4427 configs: starfive:　Enable CONFIG_OF_SEPARATE configuration See merge request sdk/u-boot!47
2023-04-10dts: pmu: remove pmu dts stall cycles config.Minda Chen1-5/+2
class 8 and class9 cpu stall cycles hwcounter is not supported in U74. delete the configuration. Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
2023-04-07Merge branch 'CR_4563_memcpy_samin.guo' into 'jh7110-master'andy.hu3-22/+103
CR4563：Configure the l2 prefetcher parameter See merge request sdk/u-boot!48
2023-04-07Merge branch 'CR_3910_Modify_cpu_vol_mason.huo' into 'jh7110-master'andy.hu2-18/+30
CR_3910 Modify cpu voltage set commands See merge request sdk/u-boot!49
2023-04-07board: starfive: jh7110: Modify cpu voltage set commandsMason Huo2-18/+30
Update the cpu voltage set commands per binning information from OTP. Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
2023-04-04riscv: dts: jh7110: Add L2 pretcher configurationSamin Guo1-0/+10
Add L2 pretcher configuration for starfive jh7110 SoC. Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2023-04-04cache: sifive: Configure the l2 prefetcher parameterSamin Guo1-0/+93
The default configuration of the SIFIVE L2 Prefetcher may not be the best combination on the JH7110, and some parameters need to be modified to achieve the best performance. Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2023-04-03board: starfive: jh7110-evb: remove l2 pretcher in borad cfgSamin Guo1-22/+0
It should be configured in L2. Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2023-03-30Merge branch 'CR_4446_pinctrl_hal.feng' into 'jh7110-master'andy.hu2-2/+20
CR 4446 pinctrl hal.feng See merge request sdk/u-boot!46
2023-03-30configs: starfive:　Enable CONFIG_OF_SEPARATE configurationYanhong Wang1-1/+2
Modify the mode of the DTB for DT Control from Embedded to separated. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
2023-03-28riscv: dts: starfive: Add gpio-controller for the gpio nodeHal Feng1-0/+2
Add gpio-controller for node gpio and gpioa. Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2023-03-28pinctrl: starfive: Add .get_function ops for the gpio driverHal Feng1-0/+16
Support getting direction of gpio. Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2023-03-28pinctrl: starfive: Fix the crash problem when using gpio cmdHal Feng1-2/+2
starfive_pinctrl_priv struct is a priv of the parent device (pinctrl device), not the gpio device. Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2023-03-20Merge branch 'CR_4136_evb_515_uboot_logo_keith.zhao' into 'jh7110-master'andy.hu1-0/+0
display: resize the bmp logo See merge request sdk/u-boot!45
2023-03-20display: resize the bmp logokeith.zhao1-0/+0
reduce the bmp size as the uboot partttion is 4M Signed-off-by: keith <keith.zhao@starfivetech.com>
2023-03-17Merge branch 'CR_4094_evb_515_uboot_logo_keith.zhao' into 'jh7110-master'andy.hu4-2/+13
CR_4094 display: update uboot logo display function: See merge request sdk/u-boot!42
2023-03-17CR_4094 display: update uboot logo display function:keith.zhao4-2/+13
2023-03-17Merge branch 'CR_3499_vout_console_515_changhuang.liang' into 'jh7110-master'andy.hu2-2/+2
CR_3499_vout_console_515_changhuang.liang configs: starfive_visionfive_defconfig: Enable console to tty1 See merge request sdk/u-boot!44
2023-03-17configs: starfive_visionfive_defconfig: Enable console to tty1Changhuang Liang2-2/+2
Enable console to tty1. Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
2023-03-17Merge branch 'CR_4082_apply_csr_patch_Andy.Hu' into 'jh7110-master'andy.hu2-3/+36
CR_4082: riscv: Fix build against binutils 2.38 See merge request sdk/u-boot!43
2023-03-17Merge branch 'CR_3910_Add_cpu_vol_mason.huo' into 'jh7110-master'andy.hu2-2/+24
CR_3910 board: starfive: jh7110: Add 1.1 & 1.02v max cpu voltage See merge request sdk/u-boot!40
2023-03-17riscv: support building double-float modulesHeinrich Schuchardt2-3/+27
The riscv32 toolchain for GCC-12 provided by kernel.org contains libgcc.a compiled for double-float. To link to it we have to adjust how we build U-Boot. As U-Boot actually does not use floating point at all this should not make a significant difference for the produced binaries. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-03-17riscv: Fix build against binutils 2.38Alexandre Ghiti1-1/+10
The following description is copied from the equivalent patch for the Linux Kernel proposed by Aurelien Jarno: >From version 2.38, binutils default to ISA spec version 20191213. This means that the csr read/write (csrr*/csrw*) instructions and fence.i instruction has separated from the `I` extension, become two standalone extensions: Zicsr and Zifencei. As the kernel uses those instruction, this causes the following build failure: arch/riscv/cpu/mtrap.S: Assembler messages: arch/riscv/cpu/mtrap.S:65: Error: unrecognized opcode `csrr a0,scause' arch/riscv/cpu/mtrap.S:66: Error: unrecognized opcode `csrr a1,sepc' arch/riscv/cpu/mtrap.S:67: Error: unrecognized opcode `csrr a2,stval' arch/riscv/cpu/mtrap.S:70: Error: unrecognized opcode `csrw sepc,a0' Signed-off-by: Alexandre Ghiti <alexandre.ghiti@canonical.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Tested-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Christian Stewart <christian@paral.in> Reviewed-by: Rick Chen <rick@andestech.com>
2023-03-09Merge branch 'CR_3347_evb_515_uboot_hdmi_logo_keith.zhao' into 'jh7110-master'andy.hu7-163/+703
CR_3347: riscv: dts: enable hdmi dts config in uboot See merge request sdk/u-boot!39
2023-03-09board: starfive: jh7110: Add 1.1 & 1.02v max cpu voltageMason Huo2-2/+24
Add two more binning IC types, and set add their max cpu voltage accordingly. Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
2023-03-08hdmi: add hdmi driver in ubootkeith.zhao5-117/+690
hdmi can show a bitmap logo while uboot start and the default resolution is 1920x1080@60fps Signed-off-by: keith.zhao<keith.zhao@statfivetech.com>
2023-03-08riscv: dts: enable hdmi dts config in ubootkeith.zhao2-46/+13
hdmi can show a bitmap logo while uboot start and the default resolution is 1920x1080@60fps Signed-off-by: keith.zhao<keith.zhao@statfivetech.com>
generated by cgit v1.2.3 (git 2.39.0) at 2024-07-14 07:25:15 +0300