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2022-02-09sata: sata_sil: Only support BLKSimon Glass1-115/+3
No boards use this driver without CONFIG_BLK, so clean up the dead code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
2022-02-09sata: Rearrange Kconfig for SATASimon Glass115-34/+151
Move the SATA options inside an 'if SATA' part, so they are grouped. Fix the 'Complient' typo while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
2022-02-09sata: Only support BLKSimon Glass2-30/+1
No boards currently use SATA without BLK: ./tools/moveconfig.py -f SATA ~BLK 0 matches Make SATA depend on BLK to avoid any future confusion. Drop the dead code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
2022-02-09sata: Drop Silicon Image SIL3114 SATA driverSimon Glass4-978/+0
This is not used in U-Boot and has not been converted to driver model. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
2022-02-09Convert CONFIG_REMAKE_ELF to KconfigAlper Nebi Yasak222-69/+187
This converts the following to Kconfig: CONFIG_REMAKE_ELF Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2022-02-09Drop CONFIG_SYS_PIO_MODESimon Glass2-6/+0
This option is not used in U-Boot. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
2022-02-09Convert CONFIG_SYS_IDE_MAXBUS et al to KconfigSimon Glass42-113/+246
This converts the following to Kconfig: CONFIG_SYS_IDE_MAXBUS CONFIG_SYS_IDE_MAXDEVICE CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_ATA_STRIDE CONFIG_SYS_ATA_DATA_OFFSET CONFIG_SYS_ATA_REG_OFFSET CONFIG_SYS_ATA_ALT_OFFSET CONFIG_SYS_ATA_IDE0_OFFSET CONFIG_SYS_ATA_IDE1_OFFSET CONFIG_ATAPI CONFIG_IDE_RESET Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
2022-02-09ide: Drop CONFIG_IDE_AHBSimon Glass3-37/+0
This is not used in U-Boot anymore. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
2022-02-09buildman: Allow adjusting board config on the flySimon Glass5-8/+93
Add a -a option to specify changes to the config before the build commences. For example buildman -a ~CONFIG_CMDLINE disables CONFIG_CMDLINE before doing the build. This makes it easier to try things out as well as to write tests without creating a new board or manually manging the .config file. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-02-09buildman: Provide a hint on how to debug thread crashesSimon Glass2-2/+4
If a thread crashes it is helpful to try the operation again with threading disabled. Add a hint about that. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-02-09buildman: Add helper functions for updating .config filesSimon Glass3-2/+360
At present the only straightforward way to write tests that need a slightly different configuration is to create a new board with its own configuration. This is cumbersome. It would be useful if buildman could adjust the configuration of a build on the fly. In preparation for this, add a utility library which can modify a .config file according to various parameters passed to it. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-02-09buildman: Make use of test_utilSimon Glass1-15/+11
Use test_util to run the tests, with the ability to select a single test to run, if desired. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-02-09buildman: Add a flag to control the tracebackSimon Glass2-0/+5
At present the full horror of the Python traceback is shown by default. It is normally only useful for debugging. Turn it off by default and add a --debug flag to enable it. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-02-09patman: Update test_util to run doc testsSimon Glass3-23/+16
At present this function does not run the doctests. Allow the caller to pass these modules in as strings. Update patman to use this. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-02-09bloblist: Update to use conditional valueSimon Glass2-14/+11
Use the new IF_ENABLED_INT() feature to avoid needing our own inline function to handle this case. Tidy up the logic to ensure that the value is only used when present. Update the 'expected' comment also. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-02-09kconfig: Add support for conditional valuesSimon Glass2-1/+41
At present if an optional Kconfig value needs to be used it must be bracketed by #ifdef. For example, with this Kconfig setup: config WIBBLE bool "Support wibbles, the world needs more wibbles" config WIBBLE_ADDR hex "Address of the wibble" depends on WIBBLE then the following code must be used: #ifdef CONFIG_WIBBLE static void handle_wibble(void) { int val = CONFIG_WIBBLE_ADDR; ... } #endif static void init_machine() { ... #ifdef CONFIG_WIBBLE handle_wibble(); #endif } Add a new IF_ENABLED_INT() to help with this. So now it is possible to write, without #ifdefs: static void handle_wibble(void) { int val = IF_ENABLED_INT(CONFIG_WIBBLE, CONFIG_WIBBLE_ADDR); ... } static void init_machine() { ... if (IS_ENABLED(CONFIG_WIBBLE)) handle_wibble(); } The value will be CONFIG_WIBBLE_ADDR if CONFIG_WIBBLE is defined and will produce a build error if not.. This allows us to reduce the use of #ifdef in the code, ensuring that the compiler still checks the code even if it is not ultimately used for a particular build. Add a CONFIG_IF_ENABLED_INT() version as well. If an attempt is made to use a value that does not exist (i.e. when the conditional is not enabled), an error about a non-existing function is generated, e.g.: common/bloblist.c:447: undefined reference to `invalid_use_of_IF_ENABLED_INT' Signed-off-by: Simon Glass <sjg@chromium.org>
2022-02-09kconfig: Update IS_ENABLED() internalsSimon Glass1-7/+5
The config_enabled() macro currently uses 0 as the default value. Update it to allow any value, so we can pass it something else, such as a non-existent function, to produce a build error if it is not defined. Also tidy up the code style for IS_ENABLED() and drop the unnecessary brackets (the value is a simple 0 or 1). Signed-off-by: Simon Glass <sjg@chromium.org>
2022-02-09mmc: fsl: Use brackets around if()Simon Glass1-1/+1
At present the IS_ENABLED() macro has extra brackets, making it possible to write: if IS_ENABLED(CONFIG_XXX) but it is a bit confusing. Add the missing brackets. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-02-09mips: Avoid using config_enabled() directlySimon Glass1-1/+1
Use IS_ENABLED() instead, which is the correct macro for checking a CONFIG option. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-02-09imx: Don't define __ASSEMBLY__ in source filesSimon Glass66-68/+1
This is supposed to be a build-system flag. Move it there so we can define it before linux/kconfig.h is included. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-02-08Merge branch '2022-02-08-TI-platform-updates'Tom Rini93-278/+17337
- J721S2 support, IPU support on DRA7, SIERRA PHY mulitlink configuration support, Nokia RX-51 DM_KEYBOARD conversion
2022-02-08Nokia RX-51: Convert to CONFIG_DM_KEYBOARDPali Rohár3-18/+34
Signed-off-by: Pali Rohár <pali@kernel.org>
2022-02-08include: configs: j721e_evm: Add support to boot ethfw core in j721eAswath Govindraju2-10/+11
Add configs to enable booting ethfw core in j721e Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08arm: dts: k3-j721e: Add support for multilink PCIe + QSGMIIAswath Govindraju3-5/+26
Add support for QSGMII multilink configuration. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08phy: cadence: Sierra: Add support for skipping configurationAswath Govindraju1-16/+42
In some cases, a single SerDes instance can be shared between two different processors, each using a separate link. In these cases, the SerDes configuration is done in an earlier boot stage. Therefore, add support to skip reconfiguring, if it is was already configured beforehand. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08phy: cadence: Sierra: Add PCIe + QSGMII PHY multilink configurationSwapnil Jakhade1-1/+377
Add register sequences for PCIe + QSGMII PHY multilink configuration. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08phy: cadence: Sierra: Add support for PHY multilink configurationsSwapnil Jakhade1-8/+145
Add support for multilink configuration of Sierra PHY. Currently, maximum two links are supported. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08phy: cadence: Sierra: Update single link PCIe register configurationSwapnil Jakhade1-3/+215
Add single link PCIe register configurations for no SSC and internal SSC. Also, add missing PMA lane registers for external SSC. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08phy: cadence: Sierra: Check PIPE mode PHY status to be ready for operationSwapnil Jakhade1-1/+40
PIPE phy status is used to communicate the completion of several PHY functions. Check if PHY is ready for operation while configured for PIPE mode during startup. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08phy: cadence: Sierra: Check cmn_ready assertion during PHY power onSwapnil Jakhade1-0/+35
Check if PMA cmn_ready is set indicating the startup process is complete. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08phy: cadence: Sierra: Add PHY PCS common register configurationsSwapnil Jakhade1-0/+38
Add PHY PCS common register configuration sequences for single link. Update single link PCIe register sequence accordingly. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08phy: cadence: Sierra: Rename some regmap variables to be in sync with Sierra ↵Swapnil Jakhade1-6/+6
documentation No functional change. Rename some regmap variables as mentioned in Sierra register description documentation. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08phy: cadence: Sierra: Add support to get SSC type from device tree.Swapnil Jakhade1-1/+5
Add support to get SSC type from DT. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08dt-bindings: phy: cadence-sierra: Add binding to specify SSC modeSwapnil Jakhade1-0/+4
Add binding to specify Spread Spectrum Clocking mode used Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08phy: cadence: Sierra: Prepare driver to add support for multilink configurationsSwapnil Jakhade1-53/+135
Sierra driver currently supports single link configurations only. Prepare driver to support multilink multiprotocol configurations along with different SSC modes. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08arm: dts: k3-j721e: Add support for PLL_CMNLC clocks in SerDes0Aswath Govindraju2-0/+34
The PLL_CMNLC clocks are modelled as a child clock device of seirra. In the function device_probe, the corresponding clocks are probed before calling the device's probe. The PLL_CMNLC mux clock can only be created after the device's probe. Therefore, move assigned-clocks and assigned-clock-parents to the link nodes in U-Boot device tree file. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08board: ti: j721e: evm.c: Add support for probing SerDes0Aswath Govindraju1-0/+37
Add support for probing, initializing and powering, SerDes0 instance. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08phy: ti: phy-j721e-wiz.c: Fix the condition for setting P_ENABLE_FORCEAswath Govindraju1-1/+1
Fix the condition for setting P_ENABLE_FORCE bit, by syncing with the driver in kernel. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08phy: cadence: Sierra: Model PLL_CMNLC and PLL_CMNLC1 as a clockAswath Govindraju1-13/+210
Sierra has two PLLs, PLL_CMNLC and PLL_CMNLC1 and each of these PLLs has two inputs, plllc_refclk (input from pll0_refclk) and refrcv (input from pll1_refclk). Model PLL_CMNLC and PLL_CMNLC1 as a clock so that it's possible to select one of these two inputs from device tree. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08phy: cadence: Sierra: Add a UCLASS_PHY device for linksAswath Govindraju1-41/+75
Add a driver of type UCLASS_PHY for each of the link nodes in the serdes instance. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08phy: cadence: Sierra: Add missing clk_disable_unprepare() in .remove callbackKishon Vijay Abraham I1-0/+2
Add missing clk_disable_unprepare() in cdns_sierra_phy_remove(). Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08phy: cadence: Sierra: Add array of input clocks in "struct cdns_sierra_phy"Kishon Vijay Abraham I1-10/+15
Instead of having separate structure members for each input clock, add an array for the input clocks within "struct cdns_sierra_phy". This is in preparation for adding more input clocks required for supporting additional clock combination. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08phy: cadence: Sierra: Move all reset_control_get*() to a separate functionKishon Vijay Abraham I1-0/+19
No functional change. Group devm_reset_control_get() and devm_reset_control_get_optional() to a separate function. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08phy: cadence: Sierra: Move all clk_get_*() to a separate functionKishon Vijay Abraham I1-22/+35
No functional change. Group all devm_clk_get_optional() to a separate function. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08phy: cadence: Sierra: Create PHY only for "phy" or "link" sub-nodesKishon Vijay Abraham I1-0/+4
Cadence Sierra PHY driver registers PHY using devm_phy_create() for all sub-nodes of Sierra device tree node. However Sierra device tree node can have sub-nodes for the various clocks in addtion to the PHY. Use devm_phy_create() only for nodes with name "phy" (or "link" for old device tree) which represent the actual PHY. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08phy: cadence: Sierra: Fix PHY power_on sequenceKishon Vijay Abraham I1-1/+6
Commit 39b823381d9d ("phy: cadence: Add driver for Sierra PHY") de-asserts PHY_RESET even before the configurations are loaded in phy_init(). However PHY_RESET should be de-asserted only after all the configurations has been initialized, instead of de-asserting in probe. Fix it here. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08phy: cadence: sierra: Fix for USB3 U1/U2 stateSanket Parmar1-13/+14
Updated values of USB3 related Sierra PHY registers. This change fixes USB3 device disconnect issue observed while enternig U1/U2 state. Signed-off-by: Sanket Parmar <sparmar@cadence.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08dts: am57xx*: Add ipu early boot DT changesKeerthy6-0/+36
Add support for ipu early boot. Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
2022-02-08arm: dts: dra7*/am57xx-idk-evm-u-boot: Add ipu early boot DT changesKeerthy5-0/+5
Add support for ipu early boot. Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
2022-02-08arm: dts: dra7: Add ipu and related nodesKeerthy1-1/+44
Add ipu and the associated nodes. Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
generated by cgit v1.2.3 (git 2.39.0) at 2024-07-12 21:53:16 +0300