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2023-04-23Merge tag 'efi-2023-07-rc1-2' of ↵Tom Rini10-84/+78
https://source.denx.de/u-boot/custodians/u-boot-efi Pull request for efi-2023-07-rc1-2 Documentation: * Describe Python coding style UEFI: * Enable tests for authenticated capsules on the sandbox * Fix pylint warnings * Correct struct efi_hii_keyboard_layout definition
2023-04-23Merge https://source.denx.de/u-boot/custodians/u-boot-riscvTom Rini66-58/+8456
* Add StarFive VisionFive v2 Board support * Support CONFIG_REMAKE_ELF * Code cleanups for RISC-V architecture
2023-04-23Merge https://source.denx.de/u-boot/custodians/u-boot-watchdogTom Rini7-3/+415
- watchdog: arm_smc_wdt: add watchdog support (Lionel) - watchdog: ftwdt010: return a previously deleted driver now ported to DM (Sergei) - watchdog: Add a watchdog driver for Raspberry Pi boards (Etienne)
2023-04-23Merge tag 'u-boot-stm32-20230419' of ↵Tom Rini12-34/+79
https://source.denx.de/u-boot/custodians/u-boot-stm configs: _ Add usb_pgood_delay for ST boards _ increase malloc size for pre-reloc for stm32mp15 _ Set CONFIG_USB_HUB_DEBOUNCE_TIMEOUT=2s for stm32mp15 dts: _ Add QSPI support on STM32MP13x SoC family _ Add FMC support on STM32MP13x SoC family drivers/machine: _ pinctrl_stm32: Add slew rate support for stm32_pinctrl_get_pin_muxing() _ spi: stm32_qspi: Remove useless struct stm32_qspi_flash _ rawnand: stm32_fmc2: remove unsupported EDO mode _ stm32mp: fix various array bounds checks
2023-04-23Merge tag 'u-boot-nand-20230422' of ↵Tom Rini1-7/+22
https://source.denx.de/u-boot/custodians/u-boot-nand-flash Pull request for u-boot-nand-20230422 Replaces a patch by Linus Walleij merged with pull request u-boot-nand-20230417, with a newer version that contains fixes for tests run by Tom Rini.
2023-04-23mtd: rawnand: nand_base: Handle algorithm selectionLinus Walleij1-4/+25
For BRCMNAND with 1-bit BCH ECC (BCH-1) such as used on the D-Link DIR-885L and DIR-890L routers, we need to explicitly select the ECC like this in the device tree: nand-ecc-algo = "bch"; nand-ecc-strength = <1>; nand-ecc-step-size = <512>; This is handled by the Linux kernel but U-Boot core does not respect this. Fix it up by parsing the algorithm and preserve the behaviour using this property to select software BCH as far as possible. Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> Acked-by: William Zhang <william.zhang@broadcom.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Tested-by: Tom Rini <trini@konsulko.com> [am335x_evm] Link: https://lore.kernel.org/all/20230407134008.1939717-3-linus.walleij@linaro.org/ Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-04-23Revert "mtd: rawnand: nand_base: Handle algorithm selection"Dario Binacchi1-9/+3
It will be replaced by a more recent version which contains fixes for tests run by Tom Rini. This reverts commit ff33d3c87c2a1ab576607c2f67a9cb7690a4e7ca. Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2023-04-21efi_loader: Fix flexible array member definitionsIlias Apalodimas1-1/+1
When a structure contains a flexible array member, it is not supposed to be included in arrays or other structs. Quoting the C spec [0] "Such a structure (and any union containing, possibly recursively, a member that is such a structure) shall not be a member of a structure or an element of an array." IOW efi_hii_keyboard_layout should not include struct efi_key_descriptor descriptors[]; since we use it at the declaration of struct efi_hii_keyboard_package. [0] https://www.dii.uchile.cl/~daespino/files/Iso_C_1999_definition.pdf chapter 6.7.2.1 Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-04-21test: fix launch_efi()Heinrich Schuchardt1-1/+3
We cannot use old_dtb in the finally block if it has not been assigned before the try block. test/py/tests/test_efi_fit.py:458:30: E0601: Using variable 'old_dtb' before assignment (used-before-assignment) Fixes: 8391f955494e ("test/py: Create a test for launching UEFI binaries from FIT images") Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-04-21sandbox: enable CONFIG_EFI_CAPSULE_AUTHENTICATEHeinrich Schuchardt2-0/+2
Without CONFIG_EFI_CAPSULE_AUTHENTICATE=y the following tests are skipped: * test/py/tests/test_efi_capsule/test_capsule_firmware_signed_fit.py * test/py/tests/test_efi_capsule/test_capsule_firmware_signed_raw.py Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-04-21test: fix pylint warning for capsule testsHeinrich Schuchardt4-76/+65
Fix pylint warnings like: * Class inherits from object * Missing module description * Missing class description * First line of comment blank * Superfluous imports Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-04-21efi_loader: remove unused efi_capsule_authenticateHeinrich Schuchardt1-6/+0
Remove an unused implementation of efi_capsule_authenticate(). Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-04-21doc: codingstyle: Python coding styleHeinrich Schuchardt1-0/+7
Indicate that we follow PEP8 and PEP257. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-04-20riscv: Support CONFIG_REMAKE_ELFSamuel Holland1-0/+2
Add flags to tell objcopy what kind of ELF to create. Signed-off-by: Samuel Holland <samuel@sholland.org>
2023-04-20riscv: Update alignment for some sections in linker scriptsBin Meng2-4/+4
Some sections in the linker scripts are aligned to 4 bytes, which may cause misaligned exception on some platforms, e.g.: clearing the bss section on 64-bit hardware if __bss_start does not start from a naturally 8 bytes aligned address. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-04-20riscv: spl: Remove relocation sectionsBin Meng2-25/+2
U-Boot SPL is not relocable. Drop these relocation sections. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-04-20riscv: Avoid updating the link registerBin Meng1-1/+1
board_init_r does not return for U-Boot SPL hence there is no need to update the link register when jumping to board_init_r. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-04-20riscv: Change to use positive offset to access relocation entriesBin Meng1-12/+7
The codes currently skip the very first relocation entry, and have an inaccurate comment "skip first reserved entry" indicating that the first entry is reserved, but later it references the elements in the first relocation entry using a minus offset. Change to use a positive offset so that there is no need to skip the first relocation entry. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-04-20makefile: riscv: Drop useless argument of prelink-riscvBin Meng1-1/+1
The argv[2] is never used in prelink-riscv. Drop it. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Rick Chen <rick@andestech.com>
2023-04-20tools: prelink-riscv: Unmap the ELF image when doneBin Meng1-0/+2
The codes forget to call munmap() to unmap the ELF image that was mapped by previous mmap(). Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Rick Chen <rick@andestech.com>
2023-04-20tools: prelink-riscv: Cosmetic style fixesBin Meng1-6/+6
Some coding convention fixes. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Rick Chen <rick@andestech.com>
2023-04-20riscv: Optimize loading relocation typeBin Meng1-1/+0
't5' already contains relocation type so don't bother reloading it. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Rick Chen <rick@andestech.com>
2023-04-20riscv: Optimize source end address calculation in start.SBin Meng1-3/+1
The __bss_start is the source end address hence load its address directly into register 't2' for optimization. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Rick Chen <rick@andestech.com>
2023-04-20riscv: Enforce DWARF4 outputBin Meng1-2/+1
Since commit 409e4b547872 ("Makefile: Enforce DWARF4 output") the whole U-Boot build switched to enforce DWARF4 output, but RISC-V is still on its own setting. Let's switch to use U-Boot's setting. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-04-20riscv: Correct a comment in io.hBin Meng1-1/+1
Replace NDS32 with RISC-V in the comments. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Rick Chen <rick@andestech.com>
2023-04-20configs: starfive: add starfive_visionfive2_defconfigYanhong Wang1-0/+79
This is the initial basic config for StarFive VisionFive v2 board. It includes consol, Norflash, sdio, ddr etc. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Tested-by: Conor Dooley <conor.dooley@microchip.com>
2023-04-20riscv: dts: jh7110: Add initial StarFive VisionFive v2 board device treeYanhong Wang6-1/+483
Add initial device tree for StarFive VisionFive v2 board. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Tested-by: Conor Dooley <conor.dooley@microchip.com>
2023-04-20riscv: dts: jh7110: Add initial u-boot device treeYanhong Wang1-0/+99
Add initial u-boot device tree for the JH7110 RISC-V SoC. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Tested-by: Conor Dooley <conor.dooley@microchip.com>
2023-04-20riscv: dts: jh7110: Add initial StarFive JH7110 device treeYanhong Wang1-0/+573
Add initial device tree for the JH7110 RISC-V SoC. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Tested-by: Conor Dooley <conor.dooley@microchip.com>
2023-04-20board: starfive: Add TARGET_STARFIVE_VISIONFIVE2 to KconfigYanhong Wang1-0/+5
Add board support for StarFive VisionFive v2. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Tested-by: Conor Dooley <conor.dooley@microchip.com>
2023-04-20board: starfive: Add Kconfig for StarFive VisionFive v2 BoardYanhong Wang1-0/+53
Add Kconfig to select the basic functions for StarFive VisionFive v2 Board. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Tested-by: Conor Dooley <conor.dooley@microchip.com>
2023-04-20riscv: cpu: jh7110: Add Kconfig for StarFive JH7110 SoCYanhong Wang1-0/+28
Add Kconfig to select the basic functions for StarFive JH7110 SoC. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Tested-by: Conor Dooley <conor.dooley@microchip.com>
2023-04-20board: starfive: add StarFive VisionFive v2 board supportYanhong Wang8-0/+692
Add board support for StarFive VisionFive v2. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Tested-by: Conor Dooley <conor.dooley@microchip.com>
2023-04-20ram: starfive: add ddr driverYanhong Wang10-1/+3202
Add driver for StarFive JH7110 to support ddr initialization in SPL. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Tested-by: Conor Dooley <conor.dooley@microchip.com>
2023-04-20pinctrl: starfive: Add StarFive JH7110 driverKuan Lim Lee8-0/+1001
Add pinctrl driver for StarFive JH7110 SoC. Signed-off-by: Kuan Lim Lee <kuanlim.lee@linux.starfivetech.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com> Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Tested-by: Conor Dooley <conor.dooley@microchip.com>
2023-04-20dt-bindings: pinctrl: Add StarFive JH7110 pinctrl definitionsJianlong Huang1-0/+427
Add pinctrl definitions for StarFive JH7110 SoC. Signed-off-by: Kuan Lim Lee <kuanlim.lee@linux.starfivetech.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com> Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Tested-by: Conor Dooley <conor.dooley@microchip.com>
2023-04-20clk: starfive: Add StarFive JH7110 clock driverYanhong Wang7-0/+1004
Add a DM clock driver for StarFive JH7110 SoC. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Tested-by: Conor Dooley <conor.dooley@microchip.com>
2023-04-20dt-bindings: clock: Add StarFive JH7110 clock definitionsYanhong Wang1-0/+257
Add all clock outputs for the StarFive JH7110 clock generator. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Acked-by: Sean Anderson <seanga2@gmail.com> Tested-by: Conor Dooley <conor.dooley@microchip.com>
2023-04-20reset: starfive: jh7110: Add reset driver for StarFive JH7110 SoCYanhong Wang3-0/+175
Add a DM reset driver for StarFive JH7110 SoC. Note that the register base address of reset controller is the same with the clock controller. Therefore, there is no device tree node alone for reset driver.It binds device node in the clock driver Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Tested-by: Conor Dooley <conor.dooley@microchip.com>
2023-04-20dt-bindings: reset: Add StarFive JH7110 reset definitionsYanhong Wang1-0/+183
Add resets for the StarFive JH7110 system(SYS),system-top-group(STG) and always-on(AON) reset controller. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Tested-by: Conor Dooley <conor.dooley@microchip.com>
2023-04-20cache: starfive: Add StarFive JH7110 supportYanhong Wang1-0/+1
This adds support for the StarFive JH7110 SoC which also feature this SiFive cache controller. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Tested-by: Conor Dooley <conor.dooley@microchip.com>
2023-04-20riscv: cpu: jh7110: Add support for jh7110 SoCYanhong Wang6-0/+166
Add StarFive JH7110 SoC to support RISC-V arch. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Reviewed-by: Rick Chen <rick@andestech.com> Tested-by: Conor Dooley <conor.dooley@microchip.com>
2023-04-19configs: stm32mp15: set CONFIG_USB_HUB_DEBOUNCE_TIMEOUT=2sPatrick Delaunay3-0/+3
With some USB devices connected on USB HUB for the STMicroelectronics boards, set the usb_pgood_delay=2 is not enough to ensure a correct detection for all cases; but it is solved with USB_HUB_DEBOUNCE_TIMEOUT=2s. For example, issue encountered with the USB flash disk: ID 058f:6387 Alcor Micro Corp. Flash Drive Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-04-19stm32mp: fix various array bounds checksRasmus Villemoes3-4/+4
In all these cases, the index on the LHS is immediately afterwards used to access the array appearing in the ARRAY_SIZE() on the RHS - so if that index is equal to the array size, we'll access one-past-the-end of the array. Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2023-04-19mtd: rawnand: stm32_fmc2: remove unsupported EDO modeChristophe Kerello1-0/+3
Remove the EDO mode support from as the FMC2 controller does not support the feature. Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-04-19ARM: dts: stm32: add FMC support on STM32MP13x SoC familyChristophe Kerello1-0/+33
Add FMC support on STM32MP13x SoC family. Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-04-19configs: stm32mp15: increase malloc size for pre-relocPatrick Delaunay1-1/+1
The early malloc usage increased so the associated defined CONFIG_SYS_MALLOC_F_LEN need to be increased. For example, for stm32mp15_defconfig and stm32mp157c-dk2-scmi.dtsi, we have: Early malloc usage: 280b8 / 80000 Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2023-04-19spi: stm32_qspi: Remove useless struct stm32_qspi_flashPatrice Chotard1-24/+3
Currently, in stm32_qspi_claim_bus(), QSPI_CR and QSPI_DCR registers are saved in stm32_ospi_flash struct on first flash memory initialization and restored on each flash accesses. As the logic of spi-uclass.c changed since 'commit 741280e9accd ("spi: spi-uclass: Fix spi_claim_bus() speed/mode setup logic")' set_speed() and set_mode() callbacks are called systematically when bus speed or bus mode need to be updated, QSPI_CR and QSPI_DCR registers are set accordingly. So stm32_qspi_claim_bus() can be updated by removing QSPI_CR and QSPI_DCR save/restore code and struct stm32_ospi_flash can be removed as well. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2023-04-19ARM: dts: stm32: Add QSPI support on STM32MP13x SoC familyPatrice Chotard1-0/+15
Add QSPI support on STM32MP13x SoC family Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2023-04-19pinctrl: pinctrl_stm32: Add slew rate support for stm32_pinctrl_get_pin_muxing()Patrice Chotard1-4/+15
For debug purpose, it should be useful to indicate the slew rate for each pins. Add ospeed register information for pins which are configured in either alternate function or gpio output. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
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