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2021-12-24configs: rock-pi-4: Enable rockchip efuse supportSjoerd Simons2-0/+2
Enable efuse support for reading the cpuid#, serial# and generate a board unique mac address Signed-off-by: Sjoerd Simons <sjoerd@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-12-24rockchip: boot_mode: fix fastboot commandJohn Keeping1-1/+1
The USB controller index must be separated from the type argument, otherwise the preboot command fails with the error: Error: Wrong USB controller index format Add the missing space to fix fastboot mode here. Signed-off-by: John Keeping <john@metanate.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-12-24power: pmic/fan53555: allow dm be omitted by SPLQuentin Schulz2-1/+15
Allow the dm driver be omitted by SPL. Cc: Quentin Schulz <foss+u-boot@0leil.net> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-12-24engicam: px30: Add Engicam PX30.Core C.TOUCH 2.0 10.1" OFJagan Teki4-0/+123
PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam. C.TOUCH 2.0 is a general purpose carrier board with capacitive touch interface support. 10.1" OF is a capacitive touch 10.1" Open Frame panel solutions. PX30.Core needs to mount on top of C.TOUCH 2.0 carrier with pluged 10.1" OF for creating complete PX30.Core C.TOUCH 2.0 10.1" Open Frame. Add support for it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-12-24arm64: dts: rockchip: Sync px30 from linux-nextJagan Teki16-255/+681
Sync the px30 devicetree files from linux-next tree. commit <14ce8069f48b> ("lib/stackdepot: allow optional init and stack_table allocation by kvmalloc() - fixup3") Note, this path even sync rk3326 files as it depends on px30. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-12-24arm64: dts: rockchip: px30: Move dmc into -u-boot.dtsiJagan Teki3-13/+12
dmc node is specific to U-Boot, it is always better practice to maintain U-Boot specific nodes into -u-boot.dtsi files in order to maintain Linux dts file sync compatibility. Move the dmc into px30-u-boot.dtsi, also add dmc node explicitly in rk3326-odroid-go2-u-boot.dtsi since it is using px30.dts. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-12-24doc: rockchip: puma: update build and flash instructionsQuentin Schulz2-55/+38
Long gone is the time a custom TF-A was needed for Puma, upstream TF-A works just fine now. The flashing instructions are updated to match how newer rkdeveloptool and rkbin work. Finally, rkbin provides a way to flash SPI via USB OTG interface so let's document that. Cc: Quentin Schulz <foss+u-boot@0leil.net> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-12-24dts: rockchip: rk3399: enable emmc phy for splYifeng Zhao1-0/+4
adapting commit ac804143cf ("mmc: rockchip_sdhci: add phy and clock config for rk3399") to fix the issue "Not found emmc phy device". Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com> Reviewed-by: Peter Robinson <pbrobinson@gmail.com> Tested-by: Peter Robinson <pbrobinson@gmail.com> - on a Rock960 Reviewed-by: Patrick Wildt <patrick@blueri.se> Tested-by: Patrick Wildt <patrick@blueri.se> - on a Pinebook Pro Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-12-24rockchip: rk3568: add arch_cpu_init()Nico Cheng1-3/+24
We configured the drive strength and security of EMMC in arch_cpu_init(). Signed-off-by: Nico Cheng <nico.cheng@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-12-24arm: dts: rockchip: rk3568: Enable sdhci and sdmmc0 nodeNico Cheng1-0/+17
Enable sdhci and sdmmc0 node in rk3568-u-boot.dtsi Signed-off-by: Nico Cheng <nico.cheng@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-12-24rockchip: Kconfig: Enable SPL support for rk3568Nico Cheng3-1/+32
Enable SPL support in Kconfig and add some related option in rk3568_common.h Signed-off-by: Nico Cheng <nico.cheng@rock-chips.com> Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-12-24rockchip: px30: add support for HW RNG for Odroid Go AdvanceChris Morgan1-0/+6
The Odroid Go Advance has a hardware random number generator present. The device does not have an upstream Linux driver, but does have a U-Boot driver. Add the appropriate node so that the hardware RNG can be used in U-Boot. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-12-24cmd: kaslrseed: add command to generate value from hwrngChris Morgan3-0/+89
Allow the kaslr-seed value in the chosen node to be set from a hardware rng source. Tested on a Rockchip PX30 (Odroid Go Advance), you must have loaded the devicetree first and prepared it for editing. On my device the workflow goes as follows: setenv dtb_loadaddr "0x01f00000" load mmc 0:1 ${dtb_loadaddr} rk3326-odroid-go2.dtb fdt addr ${dtb_loadaddr} fdt resize kaslrseed and the output can be seen here: fdt print /chosen chosen { kaslr-seed = <0x6f61df74 0x6f7b996c>; stdout-path = "serial2:115200n8"; }; Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-12-20Prepare v2022.01-rc4Tom Rini1-1/+1
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-20Revert "image: Remove #ifdefs from select_ramdisk()"Tom Rini1-72/+67
This reverts commit f33a2c1bd0fb371511a485cac1f182ba50db51be. This causes a crash on some platforms as seen here: https://lore.kernel.org/r/f153017b-c41a-0d32-67b9-f288e695f900@baylibre.com/ Reported-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-20fw_setenv: Unbreak fw_setenv caused by buggy MEMISLOCKED useJoakim Tjernlund1-7/+8
Commit "fw_setenv: lock the flash only if it was locked before" checks for Locked status with uninitialized erase data. Address by moving the test for MEMISLOCKED. Fixes: 8a726b852502 ("fw_setenv: lock the flash only if it was locked before") Signed-off-by: Joakim Tjernlund <joakim.tjernlund@infinera.com>
2021-12-20Merge tag '20211220-fixes-for-2022.01' of ↵Tom Rini1-2/+10
https://source.denx.de/u-boot/custodians/u-boot-i2c i2c changes for 20211220-fixes-for-2022.01 - mvtwsi: Swab the register address if its size is > 1
2021-12-20i2c: mvtwsi: Swab the register address if its size is > 1Stefan Roese1-2/+10
Testing on Armada XP with an EEPROM using register address with size of 2 has shown, that the register address bytes are sent to the I2C EEPROM in the incorrect order. This patch swabs the address bytes so that the correct address is transferred to the I2C device. BTW: This worked without any issues before migrating Armada XP to DM I2C. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Samuel Holland <samuel@sholland.org> Cc: Baruch Siach <baruch@tkos.co.il> Cc: Pali Rohár <pali@kernel.org> Cc: Marek Behún <marek.behun@nic.cz> Tested-by: Marek Behún <marek.behun@nic.cz>
2021-12-18Merge tag 'efi-2022-01-rc4-3' of ↵Tom Rini7-5/+119
https://source.denx.de/u-boot/custodians/u-boot-efi Pull request for efi-2022-01-rc4-3 Documentation: * add Calxeda Highbank/Midway board documentation Bug fixes: * call part_init() in blk_get_device_by_str() only for MMC * fix an 'undefined' error in some driver model macros
2021-12-18dm: fix an 'undefined' error in some macrosAKASHI Takahiro1-4/+4
Due to a non-existing parameter name in macro's, use of those macro's will cause a compiler error of "undefined reference". Unfortunately, dm test doesn't fail because a wrong name ("&dev", hence it is accidentally a valid name in the context of a caller site) is passed on. Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org> Fixes: f262d4ca4b2b ("dm: core: Add a way to read platdata for all child devices") Fixes: 903e83ee8464 ("dm: core: Add a way to iterate through children, probing each") Reviewed-by: Simon Glass <sjg@chromium.org>
2021-12-18blk: add a helper function, blk_probe_or_unbind()AKASHI Takahiro2-0/+25
This function will be commonly used in block device drivers in the succeeding patches. Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2021-12-18part: call part_init() in blk_get_device_by_str() only for MMCAKASHI Takahiro1-1/+2
In blk_get_device_by_str(), the comment says: "Updates the partition table for the specified hw partition." Since hw partition is supported only on MMC, it makes no sense to do so for other devices. Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-12-18doc: board: Add Calxeda Highbank/Midway documentationAndre Przywara3-0/+88
The Calxeda servers are using U-Boot as the primary bootloader, which was shipped as part of a firmware upgrade package. Even though the machines are considered legacy at this point, the port still works, so deserves some documentation. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-12-17Merge commit '4720b83d2c711062cfb55f03591b8f12c897d7cb' of ↵Tom Rini6-9/+260
https://github.com/tienfong/uboot_mainline
2021-12-17arm: socfpga: arria10: Enable double peripheral RBF configurationTien Fong Chee4-1/+54
Double peripheral RBF configuration are needed on some devices or boards to stabilize the IO configuration system. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Sin Hui Kho <sin.hui.kho@intel.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2021-12-17arm: socfpga: arria10: Reset MPFE NoC after program periph / combined RBFTien Fong Chee5-6/+195
This patch triggers warm reset to recover the MPFE NoC from corruption due to high frequency transient clock output from HPS EMIF IOPLL at VCO startup after peripheral RBF is programmed. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Sin Hui Kho <sin.hui.kho@intel.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2021-12-17arm: socfpga: arria10: Setting image magic value to romcode initswstate regTien Fong Chee2-2/+11
The romcode_initswstate register need to be set with FSBL_IMAGE_IS_VALID value if the current FSBL image is found valid, otherwise BootROM will look for next subsequent valid FSBL image when warm reset is triggered. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Sin Hui Kho <sin.hui.kho@intel.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2021-12-15Merge tag 'clk-2022.01-rc3' of ↵Tom Rini10-28/+59
https://source.denx.de/u-boot/custodians/u-boot-clk Clock patches for v2022.01-rc3 This adds better logging support for many CCF drivers, and clarifies some documentation regarding clk_get_rate.
2021-12-15clk: define LOG_CATEGORY for generic and ccf clocksPatrick Delaunay8-12/+39
Define LOG_CATEGORY to allow filtering with log command for generic clock and CCF clocks. This patch also change existing printf, debug and pr_ macro to log_ or dev_ macro. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Sean Anderson <seanga2@gmail.com>
2021-12-15clk: cosmetic: reorder include filesPatrick Delaunay6-15/+18
Reorder include files in the U-Boot expected order: the common.h header should always be first, followed by other headers in order, then headers with directories, then local files. It is a preliminary step for next patch. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Sean Anderson <seanga2@gmail.com>
2021-12-15clk: fix clk_get_rate() documentationGiulio Benetti1-1/+2
Improve clk_get_rate() @return documentation that otherwise is a bit ambiguous. At the moment I expect to return 0 as error since the return type is 'ulong', instead the function really returns negative value in case the corresponding function pointer is null and returns 0 if the clock is invalid. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Sean Anderson <seanga2@gmail.com>
2021-12-15Merge tag 'rpi-next-2022.01' of ↵Tom Rini2-2/+8
https://source.denx.de/u-boot/custodians/u-boot-raspberrypi - enable RPi Zero 2 W - fix MMC numbering issue - Update link to documentation
2021-12-15Merge https://source.denx.de/u-boot/custodians/u-boot-marvellTom Rini2-48/+61
- Marvell/PCI: Fix size of the configuration cache and disallow ROM BAR setting in pci_mvebu.c & pci-aardvark.c (Pali & Marek)
2021-12-15arm: a37xx: pci: Do not allow setting ROM BAR on PCI BridgePali Rohár1-24/+30
PCI Bridge which represents aardvark PCIe Root Port has Expansion ROM Base Address register at offset 0x30 but its meaning is different than PCI's Expansion ROM BAR register. Only address format of register is same. In reality, this device does not have any configurable PCI BARs. So ensure that write operation into BARs (including Expansion ROM BAR) is noop and registers always contain zero address which indicates that bars are unsupported. Fixes: cb056005dc67 ("arm: a37xx: pci: Add support for accessing PCI Bridge on root bus") Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
2021-12-15pci: pci_mvebu: Do not allow setting ROM BAR on PCI BridgePali Rohár1-24/+31
The PCI Bridge which represents mvebu PCIe Root Port has Expansion ROM Base Address register at offset 0x30 but its meaning is different that of PCI's Expansion ROM BAR register, although the address format of the register is the same. In reality, this device does not have any configurable PCI BARs. So ensure that write operation into BARs (including Expansion ROM BAR) is a noop and registers always contain zero address which indicates that BARs are unsupported. Fixes: a7b61ab58d5d ("pci: pci_mvebu: Properly configure and use PCI Bridge (PCIe Root Port)") Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
2021-12-15pci: pci_mvebu, pci_aardvark: Fix size of configuration cacheMarek Behún2-2/+2
Since u32 takes up 4 bytes, we need to divide the number of u32s by 4 for cfgcache. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
2021-12-13Merge tag 'u-boot-stm32-20211213' of ↵Tom Rini5-5/+45
https://source.denx.de/u-boot/custodians/u-boot-stm - enable KSZ90x1 PHY driver on DHCOR - DHSOM boards: - increase USB power-good delay - add update_sf script to install U-Boot into SF - increase PHY auto-negotiation timeout to 20 seconds - fix SoM and board coding strap GPIO handling # gpg verification failed.
2021-12-13ARM: stm32: Enable KSZ90x1 PHY driver on DHCORMarek Vasut1-0/+2
Enable KSZ9x01 PHY driver in DHCOR common configuration, since the AV96 board has this PHY populated on the PCB. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-12-13ARM: dts: stm32: Add custom PHY reset bindings on AV96Marek Vasut1-0/+11
The ethernet PHY must be reset on AV96, however DWMAC currently does not support the MDIO-bus PHY GPIO reset bindings and the ethernet MAC PHY reset property is going away on next DT sync. Add PHY specific reset bindings to trigger the PHY reset and fix sporadic ethernet malfunctions, until the next DT sync. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-12-13ARM: stm32: Fix SoM and board coding strap GPIO handling on DHSOMMarek Vasut1-4/+10
The variables retaining the strap values have to be initialized, always, make it so. Moreover, free the requested GPIO list at the end to avoid wasting memory. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-12-13ARM: stm32: Increase PHY auto-negotiation timeout to 20s on DHSOMMarek Vasut1-0/+3
The Micrel PHYs on known DHSOM based boards take a while to come out of reset, increase the auto-negotiation timeout to prevent it from timing out in case the ethernet is used right after the board was reset. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-12-13ARM: stm32: Add update_sf script to install U-Boot into SF on DHSOMMarek Vasut1-1/+11
Add script to read U-Boot from SD card and write it to matching locations in the SPI NOR, thus making the SPI NOR bootable. The script erases the entire SPI NOR, including U-Boot environment, to make sure the installation is clean. To retain environment from current running U-Boot, run 'saveenv' after running the 'update_sf' script. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-12-13ARM: stm32: Increase USB power-good delay on DHSOMMarek Vasut2-1/+9
The USB hub on STM32MP1 DHCOM boards needs to wait a bit longer until the USB Vbus is stable. Increase the USB power-good delay to 1 s. This adds default-undefined STM32MP_BOARD_EXTRA_ENV variable into stm32mp15_common.h to reduce duplication in board-specific config files adding custom environment. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-12-13Merge https://source.denx.de/u-boot/custodians/u-boot-shTom Rini13-145/+129
- A few clean ups for the RZG2
2021-12-13configs: beacon-rzg2m: Config to address new aliasesAdam Ford1-1/+1
The resync of the device trees from Linux 5.16-rc3 caused aliases to appear on the MMC devices which changed the numbering. This changed the default boot device and caused boot failure. Update the mmcdev variable to reflect the new aliases. Signed-off-by: Adam Ford <aford173@gmail.com>
2021-12-13ARM: rmobile: Fix rzg2_beacon_defconfig to address new aliasesAdam Ford1-1/+0
The resync of the device trees from Linux 5.16-rc3 caused aliases to appear on the MMC devices which changed the numbering. This broke the reading/writing of the environmental variables, so update the defconfig accordingly. Signed-off-by: Adam Ford <aford173@gmail.com>
2021-12-13arm: dts: Create common rz-g2-beacon-u-boot fileAdam Ford5-100/+91
The rzg2_beacon_defconfig creates an image for RZ/G2[MNH] and as such creates three different device trees and each of them have a corresponding -u-boot.dtsi file which are basically copies of each other. Create a common include file to be referenced by each of the respective board-u-boot.dtsi files to reduce duplicate code and simplify support going forward. This also restores some lost functionality from the device tree re-sync and updates the MAINTAINER file to include all beacon-renesom device tree files. Signed-off-by: Adam Ford <aford173@gmail.com>
2021-12-13arm: dts: beacon-rzg2: Resync device trees with Linux 5.16-rc3Adam Ford5-38/+32
The device trees for the Beacon RZ/G2[MNH] boards have undergone some changes over time, so resync them now. Signed-off-by: Adam Ford <aford173@gmail.com>
2021-12-13net: ravb: Support multiple clocksAdam Ford1-5/+5
The RZ/G2 series uses an external clock as a reference to the AVB. If this clock is controlled by an external programmable clock, it must be requested by the consumer or it will not turn on. In order to do this, update the driver to use bulk enable and disable functions to enable clocks for boards with multiple clocks. Signed-off-by: Adam Ford <aford173@gmail.com>
2021-12-10Merge tag 'efi-2022-01-rc4-2' of ↵Tom Rini24-44/+346
https://source.denx.de/u-boot/custodians/u-boot-efi Pull request efi-2022-01-rc4-2 UEFI: * correctly handle missing TPM device * prepare for block devices for U-Boot as EFI app # gpg: Signature made Fri 10 Dec 2021 04:29:20 AM EST # gpg: using RSA key 6DC4F9C71F29A6FA06B76D33C481DBBC2C051AC4 # gpg: Good signature from "Heinrich Schuchardt <xypron.glpk@gmx.de>" [unknown] # gpg: aka "[jpeg image of size 1389]" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6DC4 F9C7 1F29 A6FA 06B7 6D33 C481 DBBC 2C05 1AC4
generated by cgit v1.2.3 (git 2.39.0) at 2024-07-02 00:22:56 +0300