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2014-12-19x86: ifdtool: Correct a debug() missing parameterSimon Glass1-1/+2
This is missing a parameter. Fix it to avoid a warning when debug is enabled. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-12-18ARM: UniPhier: enable CONFIG_CMD_DMMasahiro Yamada1-0/+2
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-18ARM: UniPhier: select CONFIG_SPLMasahiro Yamada4-3/+1
Now UniPhier platform is only supported with SPL. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-18ARM: UniPhier: use DRAM area for init stack of normal imageMasahiro Yamada1-0/+4
The normal image is working on DRAM. It is better to use DRAM also for init stack than L2 cache. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-18ARM: UniPhier: remove unnecessary ifdef conditionalMasahiro Yamada1-4/+0
init_page_table is only set on SPL. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-18ARM: UniPhier: fix property names of aliases nodes of device treesMasahiro Yamada4-15/+15
The property name of the "aliases" node should be "serial*" to assign a desired number for the device sequence number. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-16Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini26-60/+389
2014-12-16Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini17-52/+1901
2014-12-16arm: socfpga: board: Repair Micrel PHY tuningPavel Machek1-6/+28
Add proper error checking into the PHY tuning patch. Make the PHY tunning only happen in case the KSZ9021 PHY is enabled in config. Call the config callback after the tuning finished. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@opensource.altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Tom Rini <trini@ti.com> Cc: Pavel Machek <pavel@denx.de>
2014-12-16Merge git://git.denx.de/u-boot-x86Tom Rini53-177/+2159
2014-12-15mpc85xx/t104xrdb: convert deep sleep to generic board interfaceTang Yuantian4-29/+36
A new interface is introduced to support generic board structure. Converts it to use new interface. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-15qe/deep-sleep: modify qe deep-sleep for generic boardZhao Qiang1-0/+11
Deep sleep for generic board is supported now, modify qe deep-sleep code to adapt it. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-15p5040ds: changed liodn offsetsTudor Laurentiu1-12/+12
Offsets were overlaping, causing pamu access violations in hypervised scenarios. Signed-off-by: Cristian Sovaiala <cristian.sovaiala@freescale.com> Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-15crypto/fsl: Fix RNG instantiation failure.gaurav rana1-1/+1
Corrected the order of arguments in memset in run_descriptor function. Wrong order of argumnets led to improper initialization of members of struct type result. This resulted in RNG instantiation error. Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-15powerpc/T10xx: Fix number of portalsJeffrey Ladouceur4-8/+8
Following boards has incorrect number of portals defined. powerpc/T102xQDS powerpc/T102xRDB powerpc/T1040QDS powerpc/T104xRDB Signed-off-by: Jeffrey Ladouceur <Jeffrey.Ladouceur@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-15mpc85xx: inhibit qman and bman portals by defaultJeffrey Ladouceur15-0/+267
Not all portals might be managed and therefore visible. Set the isdr register so that the corresponding isr register won't be set. This is required when supporting power management. Signed-off-by: Jeffrey Ladouceur <Jeffrey.Ladouceur@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-15net/fm: update ft_fixup_port to differentiate dual-role macShengzhou Liu1-5/+16
we need to differentiate dual-role MACs into two types: MACs with 10GEC enumeration consistent with DTSEC enumeration(defined by CONFIG_FSL_FM_10GEC_REGULAR_NOTATION) and other MACs without CONFIG_FSL_FM_10GEC_REGULAR_NOTATION defined. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-15powerpc/mpc85xx: Fix DDR TLB mapping leftoverYork Sun1-4/+8
Commit f29f804a93e87c17670607641d120f431a3b0633 generalized the TLB mapping function, but made the DDR mapping leftover size to zero, causing the message not printed. Signed-off-by: York Sun <yorksun@freescale.com> CC: Alexander Graf <agraf@suse.de> CC: Scott Wood <scottwood@freescale.com>
2014-12-15driver/ddr/fsl: Fix MRC_CYC calculation for DDR3York Sun1-1/+20
For DDR controller version 4.7 or newer, MRC_CYC (mode register set cycle time) is max(tMRD, tMOD). tMRD is 4nCK, or 8nCK (RDIMM). tMOD is max(12nCK, 15ns) according to JEDEC spec. DDR4 is not affected by this change. Signed-off-by: York Sun <yorksun@freescale.com>
2014-12-15powerpc/p2041rdb: enable generic board configsShaohui Xie1-0/+2
Add following configs in header file: CONFIG_SYS_GENERIC_BOARD CONFIG_DISPLAY_BOARDINFO Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-15powerpc/t4240rdb: Convert to use generic board codeChunhe Lan1-0/+2
Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-15powerpc/bsc913x: Convert to use generic board codeharninder rai2-0/+6
Signed-off-by: Harninder Rai <harninder.rai@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-15ARM: remove redundant asmlinkage defineMasahiro Yamada1-3/+0
Use asmlinkage defined in include/linux/linkage.h if necessary. Actually no ARM board uses asmlinkage, so this commit has no impact. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
2014-12-15x86: move arch-specific asmlinkage to <asm/linkage.h>Masahiro Yamada7-4/+13
Commit 65dd74a674d6 (x86: ivybridge: Implement SDRAM init) introduced x86-specific asmlinkage into arch/x86/include/asm/config.h. Commit ed0a2fbf14f7 (x86: Add a definition of asmlinkage) added the same macro define again, this time, into include/common.h. (Please do not add arch-specific stuff to include/common.h any more; it is already too cluttered.) The generic asmlinkage is defined in <linux/linkage.h>. If you want to override it with an arch-specific one, the best way is to add it to <asm/linkage.h> like Linux Kernel. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2014-12-14x86: Add a simple command to show FSP HOB informationBin Meng2-0/+68
FSP builds a series of data structures called the Hand-Off-Blocks (HOBs) as it progresses through initializing the silicon. These data structures conform to the HOB format as described in the Platform Initialization (PI) specification Volume 3 Shared Architectual Elements specification, which is part of the UEFI specification. Create a simple command to parse the HOB list to display the HOB address, type and length in bytes. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2014-12-14x86: Support Intel FSP initialization path in start.SBin Meng3-0/+20
Per Intel FSP architecture specification, FSP provides 3 routines for bootloader to call. The first one is the TempRamInit (aka Cache-As-Ram initialization) and the second one is the FspInit which does the memory bring up (like MRC for other x86 targets) and chipset initialization. Those two routines have to be called before U-Boot jumping to board_init_f in start.S. The FspInit() will return several memory blocks called Hand Off Blocks (HOBs) whose format is described in Platform Initialization (PI) specification (part of the UEFI specication) to the bootloader. Save this HOB address to the U-Boot global data for later use. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2014-12-14x86: Add post failure codes for bist and carBin Meng2-0/+3
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2014-12-14x86: queensbay: Adapt FSP support codesBin Meng3-18/+28
Use inline assembly codes to call FspNotify() to make sure parameters are passed on the stack as required by the FSP calling convention. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2014-12-14x86: Initial import from Intel FSP release for Queensbay platformBin Meng12-0/+1522
This is the initial import from Intel FSP release for Queensbay platform (Tunnel Creek processor and Topcliff Platform Controller Hub), which can be downloaded from Intel website. For more details, check http://www.intel.com/fsp. Note: U-Boot coding convention was applied to these codes, so it looks completely different from the original Intel release. Also update FSP support codes license header to use SPDX ID. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2014-12-14x86: ich-spi: Add Intel Tunnel Creek SPI controller supportBin Meng1-1/+2
Add Intel Tunnel Creek SPI controller support which is an ICH7 compatible device. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2014-12-14x86: Add Intel Topcliff PCH device IDsBin Meng1-0/+8
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2014-12-14x86: Add a simple superio driver for SMSC LPC47MBin Meng4-0/+143
On most x86 boards, the legacy serial ports (io address 0x3f8/0x2f8) are provided by a superio chip connected to the LPC bus. We must program the superio chip so that serial ports are available for us. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2014-12-14x86: Add Intel Crown Bay board dts fileBin Meng2-1/+55
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2014-12-14x86: ich6-gpio: Move setup_pch_gpios() to board support codesBin Meng6-51/+55
Movie setup_pch_gpios() in the ich6-gpio driver to the board support codes, so that the driver does not need to know any platform specific stuff (ie: include the platform specifc chipset header file). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2014-12-14x86: Clean up asm-offsetsBin Meng3-5/+3
Move GD_BIST from lib/asm-offsets.c to arch/x86/lib/asm-offsets.c as it is x86 arch specific stuff. Also remove GENERATED_GD_RELOC_OFF which is not referenced anymore. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2014-12-14x86: Refactor u-boot.rom build rulesBin Meng1-21/+27
Refactor u-boot.rom build rules by utilizing quiet_cmd_ and cmd_ macros. Also make writing mrc.bin and pci option rom to u-boot.rom optional and remove mrc.bin from its dependent file list as not every x86 board port needs mrc binary blob. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2014-12-14x86: ifdtool: Separate out filenames for -D and -iSimon Glass1-6/+6
To allow these options to be specified together, separate them out. Change-Id: Ib93f11cd51eb3302127f4c82936ff2b44c88d5a2 Signed-off-by: Simon Glass <sjg@chromium.org>
2014-12-14tools/ifdtool: Support writing multiple files (-w) simultaneouslyBin Meng2-7/+26
Currently ifdtool only supports writing one file (-w) at a time. This looks verbose when generating u-boot.rom for x86 targets. This change allows at most 16 files to be written simultaneously. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2014-12-14x86: Make ROM_SIZE configurable in KconfigBin Meng2-1/+78
Currently the ROM_SIZE is hardcoded to 8MB in arch/x86/Kconfig. This will not be the case when adding additional board support. Hence we make ROM_SIZE configurable (512KB/1MB/2MB/4MB/8MB/16MB) and have the board Kconfig file select the default ROM_SIZE. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2014-12-14x86: ich-spi: Set the tx operation mode for ich 7Bin Meng1-2/+7
ICH 7 SPI controller only supports byte program (02h) for SST flash. Word program (ADh) is not supported. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-12-14x86: ich-spi: Set the rx operation mode for ich 7Bin Meng1-0/+4
ICH 7 SPI controller only supports array read command (03h). Fast array read command (0Bh) is not supported. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-12-14sf: Enable byte program supportJagannadha Sutradharudu Teki4-12/+20
Enabled byte program support for sst flashes in sf. Few controllers will only support BP, so this patch gives a tx transfer flag to set the BP so-that sf will operate on byte program transfer. A new TX operation mode SPI_OPM_TX_BP is introduced for such SPI controller to use byte program op for SST flash. Signed-off-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2014-12-14spi: sf: Support byte program for sst spi flashBin Meng2-0/+33
Currently if SST flash advertises SST_WP flag in the params table the word program command (ADh) with auto address increment will be used for the flash write op. However some SPI controllers do not support the word program command (like the Intel ICH 7), the byte programm command (02h) has to be used. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-12-14spi: Fix flag collision for SST_WPSimon Glass1-1/+1
At present SECT_4K is the same as SST_WP so we cannot tell these apart. Fix this so that the table in sf_params.c can be used correctly. Reported-by: Jens Rottmann <Jens.Rottmann@adlinktech.com> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-12-14sf: Fix look for the fastest read commandJagannadha Sutradharudu Teki3-56/+60
Few of the spi controllers are only supports array slow read which is quite different behaviour compared to others. So this fix on sf will correctly handle the slow read supported controllers. Signed-off-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2014-12-14bios_emulator: Correct ordering of includesSimon Glass2-2/+2
We should include common.h before other includes. This actually causes a build error on chromebook_link. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-12-14gpio: intel_ich6: Set correct gpio output value in ich6_gpio_direction_output()Axel Lin1-0/+2
Current code does not set gpio output value in ich6_gpio_direction_output(), fix it. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Simon Glass <sjg@chromium.org>
2014-12-14x86: ich-spi: Fix a bug of reading from a non-64 bytes aligned addressBin Meng1-15/+2
The ich spi controller driver spi_xfer() tries to align reading address to 64 bytes when doing spi data in, which causes a bug of either infinite loop or a huge size memcpy(). Actually the ich spi controller does not have such requirement of 64 bytes alignment when reading data from spi slave devices. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2014-12-12Merge branch 'master' of git://git.denx.de/u-boot-mmcTom Rini5-36/+81
2014-12-12mmc: dw_mmc: Use active DDR mode flagAndrew Gabbasov1-1/+1
The card_caps bit should denote the card capability to use DDR mode, but we need the flag indicating that the DDR mode is active. Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>