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2023-02-28board: edgeble: Fix neural-compute-module-2 board nameJagan Teki1-1/+1
The board should be RV1126-NEU2 instead RV1126-ECM0. Fix the wrong name. Fixes: b8f1ca954013 ("board: rockchip: Add Edgeble Neu2 IO Board") Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28include: rk3328: Add default env for compressed kernel imagesChristopher Obbard1-1/+3
Add default memory addresses for kernel_comp_addr_r and kernel_comp_size to enable booting from a compressed kernel image. This area is temporarily used to decompress the kernel image on-the-fly. Signed-off-by: Christopher Obbard <chris.obbard@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28arm64: dts: rockchip: rk3308: Add Radxa ROCK Pi S supportAkash Gajjar4-0/+341
Add Radxa ROCK 3 Model A support. sync rk3308-rock-pi-s.dts from Linux 6.2.0-rc7. ROCK Pi S is RK3308 based SBC from radxa.com. ROCK Pi S has a, - 256MB/512MB DDR3 RAM - SD, NAND flash (optional on board 1/2/4/8Gb) - 100MB ethernet, PoE (optional) - Onboard 802.11 b/g/n wifi + Bluetooth 4.0 Module - USB2.0 Type-A HOST x1 - USB3.0 Type-C OTG x1 - 26-pin expansion header - USB Type-C DC 5V Power Supply Linux commit commit for the same, <2e04c25b1320> ("arm64: dts: rockchip: add ROCK Pi S DTS support") Signed-off-by: Akash Gajjar <gajjar04akash@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28arm64: dts: rockchip: rk3568: Add Radxa ROCK 3 Model A board supportAkash Gajjar5-1/+716
Add Radxa ROCK 3 Model A support. sync rk3568-rock-3a.dts from Linux 6.2.0-rc7 Board Specifications - Rockchip RK3568 - 2/4/8GB LPDDR4 3200MT/s - eMMC socket, SD card slot - GbE LAN - PCIe 3.0/2.0 - M.2 Connector - 3.5mm Audio jack with mic - HDMI 2.0, MIPI DSI/CSI - USB 3.0 Host/OTG, USB 2.0 Host - 40-pin GPIO expansion ports - USB Type C PD 2.0, 9V/2A, 12V/2A, 15V/2A, 20V/2A Refer Linux commit <22a442e6586c> ("arm64: dts: rockchip: add basic dts for the radxa rock3 model a") Signed-off-by: Akash Gajjar <gajjar04akash@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28binman: Mark mkimage entry missing when its subnodes is missingJonas Karlman3-1/+53
Using the mkimage entry with the multiple-data-files prop and having a missing external blob result in an unexpected ValueError exception using the --allow-missing flag. ValueError: Filename 'missing.bin' not found in input path (...) Fix this by using _pathname that is resolved by ObtainContents for blob entries, ObtainContents also handles allow missing for external blobs. Mark mkimage entry as missing and return without running mkimage when missing entries is reported by CheckMissing. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28rockchip: mkimage: Update init size limit for RK3568Jonas Karlman1-1/+1
The current init size limit of 76KiB is too big to fit in the 64KiB SRAM on RK3568, sync init size limit from vendor u-boot to fix this. Set init size limit to 60KiB (-16KiB) for RK3568. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28rockchip: mkimage: Update init size limit for RK3328Jonas Karlman1-1/+1
Latest vendor TPL for RK3328 has grown past the current init size limit of 28KiB, sync the init size limit from vendor u-boot to fix this. Set init size limit to 30KiB (+2KiB) for RK3328. This makes it possible to use latest vendor TPL on RK3328 without getting a size limit error running the mkimage command. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28Revert "board: rockchip: Fix binman_init failure on EVB-RK3568"Jonas Karlman1-1/+0
An external TPL binary is now expected to be provided using ROCKCHIP_TPL when building RK3568 targets. This reverts commit 31500e7bcfaca08ab7c2879f502a6cf852410244. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28rockchip: Use an external TPL binary on RK3568Jonas Karlman4-2/+28
Rockchip SoCs typically use U-Boot TPL to initialize DRAM, then jumps back to BootRom to load next stage, U-Boot SPL, into DRAM. BootRom then jumps to U-Boot SPL to continue the normal boot flow. However, there is no support to initialize DRAM on RK35xx SoCs using U-Boot TPL and instead an external TPL binary must be used to generate a bootable u-boot-rockchip.bin image. Add CONFIG_ROCKCHIP_EXTERNAL_TPL to indicate that an external TPL should be used. Build U-Boot with ROCKCHIP_TPL=/path/to/ddr.bin to generate a bootable u-boot-rockchip.bin image for RK3568. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Eugen Hristev <eugen.hristev@collabora.com>
2023-02-28binman: Add support for a rockchip-tpl entryJonas Karlman5-0/+62
The rockchip-tpl entry can be used when an external TPL binary should be used instead of the normal U-Boot TPL. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Eugen Hristev <eugen.hristev@collabora.com>
2023-02-28rockchip: dts: rk3328: fix sdram paramsJonas Karlman4-0/+40
The rk3328 sdram driver read sdram parameters from the devicetree into a struct rk3328_sdram_params using dev_read_u32_array. After commit 5ab30c3176bf ("ram: rockchip: Update ddr pctl regs for px30") changed the size of struct ddr_pctl_regs, a member of struct rk3328_sdram_params, U-Boot TPL can no longer initialize DRAM on RK3328. Add ten u32 to the sdram parameter array in devicetree to align with this size change. This fixes DRAM initialization on RK3328. Fixes: 5ab30c3176bf ("ram: rockchip: Update ddr pctl regs for px30") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> # roc-rk3328-cc
2023-02-28rockchip: sdram: add dram bank with usable memory beyond 4GBJonas Karlman1-3/+9
Add a second dram bank of usable memory beyond the blob of space for peripheral near 4GB. Any memory that exists beyond the 4GB mark is added to the second bank. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28rockchip: sdram: add basic support for sdram reg info version 3Jonas Karlman2-11/+26
Newer DRAM initialization blobs from vendor can encode sdram info in a new version 3 format. The new format makes use of more bits in sys_reg3 compared to the version 2 format. Add basic support for detecting the version 3 format and decoding the high bits used for ddrtype. This fixes decode of sdram size on my RK3568 boards that have LPDDR4X. Details on the new format was deciphered from vendor u-boot commit [1]. [1] https://github.com/rockchip-linux/u-boot/commit/c69667e0e2bf4290ab1f408fcde58b8806ac266b Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28rockchip: ringneck: fix SDRAM init failQuentin Schulz1-0/+1
CONFIG_RAM_PX30_DDR4 got renamed to CONFIG_RAM_ROCKCHIP_DDR4 in commit 26f92be07e2a ("ram: rockchip: Add common ddr type configs"). Since both patchsets were merged unbeknownst to the other, the conflict wasn't detected while testing each patchset individually and could only be observed after a merge to master branch. Fixes: c925be73a0a8 ("rockchip: add support for PX30 Ringneck SoM on Haikou Devkit") Cc: Quentin Schulz <foss+uboot@0leil.net> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28mmc: rockchip_dw_mmc: fix DDR52 8-bit mode handlingJohn Keeping1-0/+8
The RK3288 TRM states that, for 8-bit DDR modes: The CLKDIV register should always be programmed with a value higher than zero (0); that is, a clock divider should always be used for 8-bit DDR mode. In Linux, the driver applies this logic for all SoCs using the driver and does not distinguish RK3288, so presumably this requirement is the same for all other Rockchip SoCs using this IP. Add the necessary code to double the clock frequency when 8-bit DDR is selected. The dw_mmc core already handles setting CLKDIV correctly given the input clock and desired bus clock. Signed-off-by: John Keeping <john@metanate.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2023-02-28arm: dts: rockchip: rk3399: nanopi-r4s: Provide smbios sysinfoChristian Kohlschütter2-0/+28
Provide human-readable manufacturer and product names for the FriendlyELEC NanoPi R4S. Enable CONFIG_SYSINFO and CONFIG_SYSINFO_SMBIOS by default. Signed-off-by: Christian Kohlschütter <christian@kohlschutter.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28Prepare v2023.04-rc3Tom Rini2-2/+2
Signed-off-by: Tom Rini <trini@konsulko.com>
2023-02-27configs: Resync with savedefconfigTom Rini2-3/+2
Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
2023-02-24Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-tegraTom Rini58-309/+1051
2023-02-24Merge branch '2023-02-23-assorted-fixes'Tom Rini5-7/+16
- btrfs bugfix, silence a bunch of gcc-12.2 linker warnings finally, relax one of the trace test time requirements (so CI doesn't fail due to test being slightly slow, but still correct), and correct env on MMC and checking for where GPT can be
2023-02-23ARM: tegra20: implement BCT patchingSvyatoslav Ryhel5-4/+193
This function allows updating bootloader from u-boot on production devices without need in host PC. Be aware! It works only with re-crypt BCT. Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20 Signed-off-by: Ramin Khonsari <raminterex@yahoo.com> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23ARM: tegra30: implement BCT patchingRamin Khonsari4-0/+131
This function allows updating bootloader from u-boot on production devices without need in host PC. Be aware! It works only with re-crypted BCT. Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30 Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30 Signed-off-by: Ramin Khonsari <raminterex@yahoo.com> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23ARM: tegra: crypto: extend crypto functionalSvyatoslav Ryhel3-38/+91
Add support for encryption, decryption and signinig with non-zero key saving backward compatibility. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23ARM: tegra: expose crypto module for all Tegra SoCsSvyatoslav Ryhel6-1/+8
Move crypto module from T20 only into common Tegra dir. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23board: tegra30: switch to updated pre-dm i2c writeSvyatoslav Ryhel12-46/+200
Configure PMIC voltages for early stages using updated early i2c write. Tested-by: Thierry Reding <treding@nvidia.com> # Beaver T30 Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23board: tegra124: switch to updated pre-dm i2c writeSvyatoslav Ryhel4-145/+88
Configure PMIC for early stages using updated i2c write. Tested-by: Thierry Reding <treding@nvidia.com> # Jetson TK1 T124 Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23ARM: tegra: create common pre-dm i2c writeSvyatoslav Ryhel4-26/+33
This implementation allows pwr i2c writing on early SPL stages when DM is not yet setup. Such writing is needed to configure main voltages of PMIC on early SPL for bootloader to boot properly. Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30 Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20 Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30 Tested-by: Thierry Reding <treding@nvidia.com> # T30 and T124 Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23ARM: tegra: add late init supportSvyatoslav Ryhel2-0/+8
Late init function allows passing values like identifiers and perform device specific configurations of pre-boot stage. Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30 Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30 Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23ARM: tegra: provide default USB gadget setupMaxim Schwalm11-30/+3
All Nvidia boards use the same manufacturer, vendor ID and product ID for the gadgets. Make them the defaults to remove some boilerplate from the defconfigs. Inspired by commit e02687bda96c ("sunxi: provide default USB gadget setup") which did the same for Allwinner boards. Tested-by: Thierry Reding <treding@nvidia.com> # T30 and T124 Signed-off-by: Maxim Schwalm <maxim.schwalm@gmail.com> Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23spi: tegra20_slink: accept any word lengthSvyatoslav Ryhel1-8/+11
Original t20 slink could work with commands only fully divisible by 8. This patch removes such restriction, so commands of any bitlength now can be passed and processed. Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF600T T30 Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30 Tested-by: Thierry Reding <treding@nvidia.com> # T30 and T124 Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23ARM: tegra: Fix Tegra PWM parent clockSvyatoslav Ryhel8-11/+13
Default parent clock for the PWM on Tegra is a 32kHz clock and is unable to support the requested PWM period. Fix PWM support on Tegra20, Tegra30, Tegra114, Tegra124 and Tegra210 by updating the parent clock for the PWM to be the PLL_P. This commit is equivalent to Linux kernel commit: https://lore.kernel.org/all/20221010100046.6477-1-jonathanh@nvidia.com/ Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30 Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20 Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # ASUS TF201 T30 Tested-by: Thierry Reding <treding@nvidia.com> # T30 and T124 Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23ARM: tegra30: add PLLD to pll setupSvyatoslav Ryhel1-0/+41
On T30 unlike T20 dsi panels are wider used on devices and PLLD is used as DISP1 parent more often, so lets enable it as well for this cases. Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF700T T30 Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # HTC One X T30 Tested-by: Thierry Reding <treding@nvidia.com> # Beaver T30 Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23ARM: tegra: clock: add clock_decode_pair helperSvyatoslav Ryhel2-0/+36
Get periph clock id and its parent from device tree. This works by looking up the peripheral's 'clocks' node and reading out the second and fourth cells, which are the peripheral and PLL clock numbers. Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30 Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20 Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # HTC One X Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23ARM: tegra: clock: add clk_id_to_pll_id helperSvyatoslav Ryhel6-0/+194
This function allows to convert a device tree clock ID to PLL ID. Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30 Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20 Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # HTC One X Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23ARM: t20/t30: swap host1x and disp1 clock parentsSvyatoslav Ryhel2-4/+4
According to mainline clock tables and TRM HOST1X parent is PLLC, while DISP1 usually uses PLLP as parent clock. Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30 Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20 Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30 Tested-by: Thierry Reding <treding@nvidia.com> # Beaver T30 Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23tegra30: clock: add EXTPERIPHSvyatoslav Ryhel2-6/+6
This mappings were missing for some reason. Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30 Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom <twarren@nvidia.com>
2023-02-23env: mmc: Apply GPT only on eMMC user HW partitionMarek Vasut1-4/+8
Apply the GPT U-Boot environment GUID type look up only on eMMC user HW partition, do not apply the look up on eMMC boot HW partitions as mmc_offset_try_partition() assumes either SD partitions or eMMC user HW partition. This fixes environment operation on systems where CONFIG_SYS_MMC_ENV_PART is non-zero and CONFIG_SYS_REDUNDAND_ENVIRONMENT is set. Fixes: 80105d8fd52 ("env: mmc: select GPT env partition by type guid") Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
2023-02-23trace: Relax test requirementsSimon Glass1-2/+3
We expect the profile and bootstage to agree on timing, but when running on slow machines there can be a larger descrepency. Increase the tolerance to fix this. Fixes: 9cea4797aeb ("trace: Add a test") Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-23x86: Pass -z execstack for EFI payload flagsTom Rini1-1/+2
To match how we link EFI executables elsewhere, and to silence a linker warning, pass -z execstack here as well. Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Tom Rini <trini@konsulko.com>
2023-02-23Makefile: Link with -z noexectackTom Rini1-0/+1
When moving to gcc-12.2 we started trying to quiet some of the new linker warnings, that are not relevant to us. However, a misunderstanding of the mechanics at play meant that I intentionally omitted passing -z noexecstack to the linker, when we do need to. Add this flag and in turn remove warnings from the linker. Fixes: 1e1c51f8ace8 ("Makefile: link with --no-warn-rwx-segments") Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-02-23fs: btrfs: limit the mapped length to the original lengthQu Wenruo1-0/+2
[BUG] There is a bug report that btrfs driver caused hang during file read: This breaks btrfs on the HiFive Unmatched. => pci enum PCIE-0: Link up (Gen1-x8, Bus0) => nvme scan => load nvme 0:2 0x8c000000 /boot/dtb/sifive/hifive-unmatched-a00.dtb [hangs] [CAUSE] The reporter provided some debug output: read_extent_data: cur=615817216, orig_len=16384, cur_len=16384 read_extent_data: btrfs_map_block: cur_len=479944704; ret=0 read_extent_data: ret=0 read_extent_data: cur=615833600, orig_len=4096, cur_len=4096 read_extent_data: btrfs_map_block: cur_len=479928320; ret=0 Note the second and the last line, the @cur_len is 450+MiB, which is almost a chunk size. And inside __btrfs_map_block(), we limits the returned value to stripe length, but that's depending on the chunk type: if (map->type & (BTRFS_BLOCK_GROUP_RAID0 | BTRFS_BLOCK_GROUP_RAID1 | BTRFS_BLOCK_GROUP_RAID1C3 | BTRFS_BLOCK_GROUP_RAID1C4 | BTRFS_BLOCK_GROUP_RAID5 | BTRFS_BLOCK_GROUP_RAID6 | BTRFS_BLOCK_GROUP_RAID10 | BTRFS_BLOCK_GROUP_DUP)) { /* we limit the length of each bio to what fits in a stripe */ *length = min_t(u64, ce->size - offset, map->stripe_len - stripe_offset); } else { *length = ce->size - offset; } This means, if the chunk is SINGLE profile, then we don't limit the returned length at all, and even for other profiles, we can still return a length much larger than the requested one. [FIX] Properly clamp the returned length, preventing it from returning a much larger range than expected. Reported-by: Andreas Schwab <schwab@linux-m68k.org> Signed-off-by: Qu Wenruo <wqu@suse.com>
2023-02-22Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-usbTom Rini1-19/+19
- DWC3 bugfix
2023-02-22Merge https://source.denx.de/u-boot/custodians/u-boot-socfpgaTom Rini11-7/+47
- chameleonv3 updates
2023-02-22chameleonv3: Convert CONFIG_SPL_MAX_SIZE to KconfigPaweł Anikiel1-0/+1
This file was missed during the conversion process. Add the symbol to defconfig. Signed-off-by: Paweł Anikiel <pan@semihalf.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-02-22arm: dts: chameleonv3: Add 270-2 variantPaweł Anikiel3-0/+18
Add devicetree for chameleonv3 with the 270-2I2-D11E variant of the Mercury+ AA1 module Signed-off-by: Paweł Anikiel <pan@semihalf.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-02-22arm: dts: chameleonv3: Rename chameleonv3.dts to .dtsiPaweł Anikiel3-2/+2
This file is included by the different chameleonv3 variants. Change the name to .dtsi. Signed-off-by: Paweł Anikiel <pan@semihalf.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-02-22arm: dts: chameleonv3: Override chameleonv3 bitstream namesPaweł Anikiel2-0/+8
Set the bitstream name per Chameleon variant. This allows the same boot filesystem with all bitstream variants to be used on different boards. Signed-off-by: Paweł Anikiel <pan@semihalf.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-02-22socfpga: chameleonv3: Move environment to a text filePaweł Anikiel2-5/+17
Move the environment to an easily editable text file in the boot partition Signed-off-by: Paweł Anikiel <pan@semihalf.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-02-22socfpga: chameleonv3: Enable ext4 in SPLPaweł Anikiel1-0/+1
Allow SPL to boot from an ext4 filesystem. Signed-off-by: Paweł Anikiel <pan@semihalf.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-02-22usb: dwc3: Use the devm_gpiod_get_optional() API for reset gpioVenkatesh Yadav Abbarapu1-19/+19
As the "reset-gpios" property is optional, don't return the error and just skip the gpio reset sequence. Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
generated by cgit v1.2.3 (git 2.39.0) at 2024-08-28 01:15:21 +0300