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2019-07-17mmc: sdhci: Make set_ios_post() return intFaiz Abbas3-3/+5
Make set_ios_post() return int to faciliate error handling in platform drivers. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2019-07-17arm: dts: k3: Add phy specific properties to SD card nodeFaiz Abbas2-0/+4
With changes in the driver requiring phy related properties, add the same for the SD card node to prevent breaking boot with the driver update. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-07-17mmc: sdhci: Make sdhci_set_clock() non staticFaiz Abbas2-1/+2
The am654_sdhci driver needs to switch the clock off before disabling its phy dll and needs to re-enable the clock before enabling the phy again. Therefore, make the sdhci_set_clock() function accessible in the am654_sdhci driver. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-07-17mmc: sdhci: Add support for sdhci-caps-maskFaiz Abbas1-3/+15
Add Support for masking some bits in the capabilities register of a host controller. Also remove the redundant readl() into caps1. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-07-17regmap: Add API regmap_init_mem_index()Faiz Abbas2-0/+44
In device nodes with more than one entry in the reg property, it is sometimes useful to regmap only of the entries. Add an API regmap_init_mem_index() to facilitate this. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-07-17mmc: am654_sdhci: Remove quirksFaiz Abbas1-3/+0
The host controller works perfectly well without having to add any quirks. Remove them. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-07-17arm64: dts: k3: Sync sdhci0 node from kernel and change driver nameFaiz Abbas9-49/+116
Sync the sdhci0 node from kernel. This changes the compatible that is required to be there in the driver. Change the same for the SD card node which is not yet supported in kernel. This also syncs the main_pmx0 node as a side effect. Also change the name of the driver to match the compatible in kernel. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-07-16Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-sunxiTom Rini165-328/+719
- Beelink-x2 STB support (Marcus) - H6 DDR3, LPDDR3 changes (Andre, Jernej) - H6 pin controller, USB PHY (Andre)
2019-07-16sunxi: H6: Enable USB for existing boardsAndre Przywara5-0/+10
So far USB was not enabled for the Allwinner H6 boards, as the PHY driver was not ready and the clock gates were missing. Since this is now fixed, let's add the PHY and the OHCI/EHCI drivers to the build, for all existing H6 boards. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com> # Pine-H64 Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-07-16sunxi: phy: Add USB PHY support for Allwinner H6Andre Przywara1-0/+20
The USB PHY used in the Allwinner H6 SoC has some pecularities (as usual), which require a small addition to the USB PHY driver: In this case the second PHY is PHY3, not PHY1, so we need to skip number 1 and 2 in the code. Just use the respective code from Linux for that. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com> # Pine-H64 Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-07-16sunxi: clocks: Add H6 USB clock gates and resetsAndre Przywara1-0/+29
To enable USB support in U-Boot, add the required clock and reset gates to the H6 clock driver. Once enabled, the generic EHCI/OCHI drivers will pick them up from there automatically. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com> # Pine-H64 Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-07-16sunxi: gpio: Enable support for H6 pin controllerAndre Przywara1-0/+2
The Allwinner H6 pin controller is not really special, at least not when it comes to normal GPIO operation. Add the H6 compatible strings to the list of recognised strings, to make GPIOs work for H6 boards. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com> # Pine-H64 Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-07-16sunxi: move SUNXI_GPIO to KconfigAndre Przywara4-4/+7
Probably for no particular reason SUNXI_GPIO was still defined the "old way", in header files only. Introduce SUNXI_GPIO to the Kconfig file in drivers/gpio to remove another line from our dreadful config_whitelist.txt. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com> # Pine-H64 Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-07-16sunxi: H6: Add DDR3 DRAM delay valuesJernej Skrabec1-6/+17
Add some basic line delay values to be used with DDR3 DRAM chips on some H6 TV boxes. Taken from a register dump after boot0 initialised the DRAM. Put them as the default delay values for DDR3 DRAM until we know better. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-07-16sunxi: H6: Add DDR3-1333 timingsAndre Przywara3-0/+153
Add a routine to program the timing parameters for DDR3-1333 DRAM chips connected to the H6 DRAM controller. The values were gathered from doing back-calculations from a register dump, trying to match them up with the official JEDEC DDDR3 spec. If in doubt, the register dump values were taken for now, but the JEDEC recommendation were added as a comment. Many thanks to Jernej for contributing fixes! Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-07-16sunxi: H6: Add DDR3 support to DRAM controller driverAndre Przywara2-28/+62
At the moment the H6 DRAM driver only supports LPDDR3 DRAM. Extend the driver to cover DDR3 DRAM as well. The changes are partly motivated by looking at the ZynqMP register documentation, partly by looking at register dumps after boot0/libdram has initialised the controller. Many thanks to Jernej for contributing some fixes! Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-07-16sunxi: H6: move LPDDR3 timing definition into separate fileAndre Przywara10-148/+177
Currently the H6 DRAM driver only supports one kind of LPDDR3 DRAM. Split the timing parameters for this LPDDR3 configuration into a separate file, to allow selecting an alternative later at compile time (as the sunxi-dw driver does). Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-07-16sunxi: H6: DRAM: follow recommended PHY init algorithmAndre Przywara1-1/+3
The DRAM controller manual suggests to first program the PHY initialisation parameters to the PHY_PIR register, and then set bit 0 to trigger the initialisation. This is also used in boot0. Follow this recommendation by setting bit 0 in a separate step. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-07-16sunxi: H6: DRAM: avoid memcpy() on MMIO registersAndre Przywara1-2/+4
Using memcpy() is, however tempting, not a good idea: It depends on the specific implementation of memcpy, also lacks barriers. In this particular case the first registers were written using 64-bit writes, and the last register using four separate single-byte writes. Replace the memcpy with a proper loop using the writel() accessor. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-07-16Merge branch 'master' of git://git.denx.de/u-boot-netTom Rini32-625/+1506
2019-07-15net: macb: Add support for 1000-baseXRadu Pirea1-2/+4
Macb can be used with Xilinx PCS/PMA PHY in fpga which is a 1000-baseX phy(lpa 0x41e0). This patch adds checks for LPA_1000XFULL and LPA_1000XHALF bits. Signed-off-by: Radu Pirea <radu_nicolae.pirea@upb.ro> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-15net: macb: Fixed reading MII_LPA registerRadu Pirea1-1/+1
If macb is gem and is gigabit capable, lpa value is not read from the right register(MII_LPA) and is read from MII_STAT1000. This patch fixes reading of the lpa value. Signed-off-by: Radu Pirea <radu_nicolae.pirea@upb.ro> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-15configs: am65x_evm_a53: enable networkingGrygorii Strashko1-0/+6
Enable TI K3 AM65x CPSW NUSS driver. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-07-15arm64: dts: k3-am654-base-board: add mcu cpsw nuss pinmux and phy defsGrygorii Strashko1-0/+59
Add mcu cpsw nuss pinmux and phy defs required by cpsw. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-15arm64: dts: ti: k3-am65: add mcu cpsw nodeGrygorii Strashko2-0/+113
Add mcu cpsw and its components along with scm_conf node to have ethernet functional. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-15net: ethernet: ti: Introduce am654 gigabit eth switch subsystem driverKeerthy3-0/+801
Add new driver for the TI AM65x SoC Gigabit Ethernet Switch subsystem (CPSW NUSS). It has two ports and provides Ethernet packet communication for the device and can be configured as an Ethernet switch. CPSW NUSS features: the Reduced Gigabit Media Independent Interface (RGMII), Reduced Media Independent Interface (RMII), and the Management Data Input/Output (MDIO) interface for physical layer device (PHY) management. The TI AM65x SoC has integrated two-port Gigabit Ethernet Switch subsystem into device MCU domain named MCU_CPSW0. One Ethernet port (port 1) with selectable RGMII and RMII interfaces and an internal Communications Port Programming Interface (CPPI) port (Host port 0). Host Port 0 CPPI Packet Streaming Interface interface supports 8 TX channels and on RX channels operating by TI am654 NAVSS Unified DMA Peripheral Root Complex (UDMA-P) controller. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-15driver: net: ti: cpsw-mdio: use phys_addr_t for mdio_base addrKeerthy2-3/+3
Use phys_addr_t for mdio_base address to avoid build warnings on arm64 and dra7. Cast it to uintprt_t before assigning to regs. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-15net: phy: cortina: Use block layer to read from mmcYinbo Zhu1-0/+5
This patch is to use block layer to read from mmc in cortina Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-15net: mscc: refactor mscc_miimHoratiu Vultur8-516/+63
Because all MSCC SoC use the same MDIO bus, put the implementation in one common file(mscc_miim) and make all the other MSCC network drivers to use these functions. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-15test: dm: add MDIO testAlex Marginean7-0/+163
A very simple test for DM_MDIO, mimicks a register write/read through the sandbox bus to a dummy PHY. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-15net: introduce MDIO DM class for MDIO devicesAlex Marginean6-0/+184
Adds UCLASS_MDIO DM class supporting MDIO buses that are probed as stand-alone devices. Useful in particular for systems that support DM_ETH and have a stand-alone MDIO hardware block shared by multiple Ethernet interfaces. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-15net: mscc: serval: Remove delay when serdes is configuredHoratiu Vultur1-2/+0
When serdes configuration was written in hardware there was a delay of 100ms to be sure that configuration was written. But the delay is not needed because already the function serdes_write it is checking that the operation finished. Therefore remove the mdelay. This improves the speed of configuring the network driver. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-15net: phy: ti: Fix clock output DT propertyTrent Piepho1-8/+2
The code block reading the DT property for the clock output control was before the phy's DT node pointer was set, so it could never work. Move it after the node pointer is set. Also store the unsigned 32-bit property into an unsigned value, not a signed value, as the former will cause a problem if value overflows. For instance, if one were to add 0xffffffff as a code to mean the clock output should be turned off. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Janine Hagemann <j.hagemann@phytec.de> Cc: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Trent Piepho <tpiepho@impinj.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-15net: phy: ti: Use default values for tx/rx delay and fifo sizeTrent Piepho1-3/+3
When not using DM_ETH, these PHY settings are programmed with default values hardcoded into the driver. When using DM_ETH, they should come from the device tree. However, if the device tree does not have the properties, the driver will silent use -1. Which is entirely out of range, programs nonsense into the PHY's registers, and does not work. Change this to use the same defaults as non-DM_ETH if the device tree is lacking the properties. As an alternative, the kernel driver for the phy will display an error message and fail if the device tree is lacking. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Janine Hagemann <j.hagemann@phytec.de> Cc: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Trent Piepho <tpiepho@impinj.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-15cmd: mii: Add the standard 1000BASE-T registersTrent Piepho1-5/+29
These are standard across gigabit phys. These mostly extend the auto-negotiation information with gigabit fields. Signed-off-by: Trent Piepho <tpiepho@impinj.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-15cmd: mii: Refactor some of the MII reg dump codeTrent Piepho1-85/+70
Share the code that prints out a register field with the function that prints out the "special" fields. There were two arrays the register dump list, one with reg number and name, another with a pointer to the field table and the table size. These two arrays had have each entry match what register is referred to. Combine them into just one table. Now they can't not match and there is just one table. Add some missing consts to pointers to string literals. The dump code was ignoring the regno field in the description table and assuming register 0 was at index 0, etc. Have it use the field. Change reg > max+1 into reg >= max, which doesn't fail if max+1 could overflow, besides just making more sense. Signed-off-by: Trent Piepho <tpiepho@impinj.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-07-15Merge tag 'mmc-2019-7-15' of https://gitlab.denx.de/u-boot/custodians/u-boot-mmcTom Rini17-419/+659
- mmc spi driver model support - drop mmc_spi command - enhanced Strobe mmc HS400 support - minor mmc bug/fixes and optimization - omap hsmmc and mvbeu update - sdhci card detect support
2019-07-15sun8i: h3: Add support for the Beelink-x2 STBMarcus Cooper4-0/+239
The Beelink X2 is an STB based on the Allwinner H3 SoC with a uSD slot, 2 USB ports( 1 * USB-2 Host, 1 USB OTG), a 10/100M ethernet port using the SoC's integrated PHY, Wifi via an sdio wifi chip, HDMI, an IR receiver, a dual colour LED and an optical S/PDIF connector. Linux commit details about the sun8i-h3-beelink-x2.dts sync: "ARM: dts: sun8i: h3: Add ethernet0 alias to Beelink X2" (sha1: cc4bddade114b696ab27c1a77cfc7040151306da) Signed-off-by: Marcus Cooper <codekipper@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-07-15sunxi: move CONFIG_SPL_TEXT_BASE from *_defconfig to KconfigAndre Przywara147-146/+3
The choice of the SPL_TEXT_BASE is not really a decision that should be specified by each board's defconfig, as this setting is actually dictated by the SoC's memory map and the BootROM behaviour. To make this obvious and reduce the clutter in the defconfig files, let's specify the SoC constraints in the Kconfig stanza. This allows us to remove these lines from the defconfig files again. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-07-15mmc: fsl_esdhc_imx: enlarge mmc timeoutPeng Fan1-2/+2
Flash system partition with fastboot will earse the partition firstly The 600ms timeout will fail on some SD Card. Enlarge it to 5s to make it works for most of sdcard Cc: guoyin.chen <guoyin.chen@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-15mmc: fsl_esdhc_imx: add i.MX8QM compatiblePeng Fan1-0/+7
Add i.MX8QM compatible and soc data, the soc data is following Linux i.MX SDHC driver. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-15mmc: fsl_esdhc_imx: add HS400 Enhanced strobe supportPeng Fan1-0/+20
Implement set_enhanced_strobe hook for fsl_esdhc_imx, ,in esdhc_set_timing and esdhc_change_pinstate, also handle HS400_ES. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-15mmc: fsl_esdhc_imx: use mmc_of_parse to set host_capsPeng Fan1-9/+5
Use mmc_of_parse to set host_caps. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-15mmc: Parse no-1-8-v DT propertyPeng Fan1-0/+5
Parse no-1-8-v DT Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
2019-07-15mmc: Parse HS400 Enhanced strobe DT propertiesPeng Fan1-0/+2
Add HS400 Enhanced strobe properties parsing support to mmc_of_parse(). Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
2019-07-15mmc: support hs400 enhanced strobe modePeng Fan4-1/+115
eMMC 5.1+ supports HS400 Enhances Strobe mode without the need for tuning procedure. The flow is as following: - set HS_TIMIMG (Highspeed) - Host change freq to <= 52Mhz - set the bus width to Enhanced strobe and DDR8Bit(CMD6), EXT_CSD[183] = 0x86 instead of 0x80 - set HS_TIMING to 0x3 (HS400) - Host change freq to <= 200Mhz - Host select HS400 enhanced strobe complete Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-15mmc: fsl_esdhc_imx: fix config check issue when building in SPLYe Li1-2/+2
Should use CONFIG_IS_ENABLED not IS_ENABLED for clock and regulator drivers, CONFIG_IS_ENABLED will check the CONFIG_SPL_CLK and CONFIG_SPL_DM_REGULATOR when building SPL. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-07-15cmd: Remove mmc_spi commandAnup Patel5-100/+0
The mmc_spi command was added to manually setup MMC over SPI bus using command. This was required by the legacy non-DM MMC_SPI driver. With DM based MMC_SPI driver in-place, we can now use all general storge commands and mmc command for MMC over SPI bus hence we remove the mmc_spi command all it's references. Suggested-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-07-15mmc: mmc_spi: Re-write driver using DM frameworkBhargav Shah3-173/+320
This patch rewrites MMC SPI driver using U-Boot DM framework and get it's working on SiFive Unleashed board. Signed-off-by: Bhargav Shah <bhargavshah1988@gmail.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-07-15mmc: skip select_mode_and_width for MMC SPI hostAnup Patel1-0/+14
The MMC mode and width are fixed for MMC SPI host hence we skip sd_select_mode_and_width() and mmc_select_mode_and_width() for MMC SPI host. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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