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2019-02-09board/BuR/brppt1: drop DM_I2C_COMPATHannes Schmelzer7-11/+8
The TPS62517 PMIC driver has been partially converted to DM, so the legacy I2C access layer isn't needed anymore. Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
2019-02-09mmc: omap_hsmmc: Workaround errata regarding SDR104/HS200 tuning failures (i929)Faiz Abbas1-1/+91
Errata i929 in certain OMAP5/DRA7XX/AM57XX silicon revisions (SPRZ426D - November 2014 - Revised February 2018 [1]) mentions unexpected tuning pattern errors. A small failure band may be present in the tuning range which may be missed by the current algorithm. Furthermore, the failure bands vary with temperature leading to different optimum tuning values for different temperatures. As suggested in the related Application Report (SPRACA9B - October 2017 - Revised July 2018 [2]), tuning should be done in two stages. In stage 1, assign the optimum ratio in the maximum pass window for the current temperature. In stage 2, if the chosen value is close to the small failure band, move away from it in the appropriate direction. References: [1] http://www.ti.com/lit/pdf/sprz426 [2] http://www.ti.com/lit/pdf/SPRACA9 Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2019-02-09clk: stm32mp1: correctly handle Clock Spreading GeneratorPatrick Delaunay2-6/+12
To activate the csg option, the driver need to set the bit2 of PLLNCR register = SSCG_CTRL: Spread Spectrum Clock Generator of PLLn enable. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-02-09dts: stm32mp1: clock tree updatePatrick Delaunay2-15/+15
- Add st,digbypass on clk_hse node (needed for board rev.C) - MLAHB/AHB max frequency increased from 200 to 209MHz, with: - PLL3P set to 208.8MHz for MCU sub-system - PLL3Q set to 24.57MHz for 48kHz SAI/SPI2S - PLL3R set to 11.29MHz for 44.1kHz SAI/SPI2S - PLL4P set to 99MHz for SDMMC and SPDIFRX - PLL4Q set to 74.25MHz for EVAL board Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-02-09clk: stm32mp1: add debug informationPatrick Delaunay2-4/+80
Add support of clk dump command and display information during probe (under CONFIG_DISPLAY_CPUINFO). Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-02-09clk: stm32mp1: recalculate counter when switching freqPatrick Delaunay1-2/+7
Because stgen is initialized with HSI clock, we need to recalculate the counter when changing frequency. Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-02-09clk: stm32mp1: correct access to RCC_OCENSETR/RCC_OCENCLRRPatrick Delaunay1-8/+5
Remove unnecessary setbits on set/clear registers. Avoid to deactivate HSI with HSE. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-02-09clk: stm32mp1: add IPCC clockPatrick Delaunay1-0/+1
Add support for enable/disable of IPCC clock using AHB3 registers Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-02-09clk: stm32mp1: no more get ck_usbo_48m in device treePatrick Delaunay1-3/+3
Remove support of ck_usbo_48m clock node in device tree, but force 48MHz frequency to prepare alignment with kernel device tree. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-02-09drivers: serial: dm: Enable DM_FLAG_PRE_RELOC in SBSA pl011 uart driverVabhav Sharma1-2/+0
The DM_FLAG_PRE_RELOC shall be enabled in SBSA PL011 uart driver as this driver is used in NXP based SoCs It is necessary to have Serial console running before relocation The !CONFIG_IS_ENABLED(OF_CONTROL) [*] check is set as "workaround" for DM problem : 4687919684e This flag is set if board does not support device-tree and using platform data, In DM Model either of device tree or platform data can be used to fetch device configuration It is possible to use SBSA UART with CONFIG_DM_SERIAL but witout corresponding device tree description (OF_CONTROL) Other board/SoCs have this flag set unconditionally Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
2019-02-09hashtable: fix environment variable corruptionRoman Kapl3-3/+136
Only first previously deleted entry was recognized, leading hsearch_r to think that there was no previously deleted entry. It then conluded that a free entry was found, even if there were no free entries and it overwrote a random entry. This patch makes sure all deleted or free entries are always found and also introduces constants for the 0 and -1 numbers. Unit tests to excersise a simple hash table usage and catch the corruption were added. To trash your environment, simply run this loop: setenv i 0 while true; do setenv v_$i $i setenv v_$i setexpr i $i + 1 done Signed-off-by: Roman Kapl <rka@sysgo.com>
2019-02-09moveconfig: add a second pass for empty #if/#endif blocksChris Packham1-2/+25
Moveconfig already attempts to remove empty #if/#endif blocks when there is a matching CONFIG_ being moved. Add a second pass which covers files without a match. Signed-off-by: Chris Packham <judge.packham@gmail.com>
2019-02-09omap3_cairo: remove empty #ifdef/#endif blockChris Packham1-10/+0
The content between these guards was removed in commit 9baa2bce2890 ("Removed unused references to CONFIG_SERIALx"). Remove the now empty #ifdef/#endif block and the accompanying comment. Signed-off-by: Chris Packham <judge.packham@gmail.com>
2019-02-09test: provide unit test for memory functionsHeinrich Schuchardt7-0/+245
Memory functions may have architecture specific implementations. These should be tested. Provide unit tests for memset(), memcpy(), memmove(). Provide a 'ut lib' sub-command to execute the tests. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-02-09doc: ti-secure: Add ULO info for AM57xx/DRA7xx secure devices from TIAndrew F. Davis1-2/+6
Booting from UART and USB on HS devices is now supported for this platform. Update documentation for the same. Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-02-09defconfigs: Add config for AM57xx High Security EVM with USB/UART Boot supportAndrew F. Davis2-0/+99
Add a new defconfig file for the AM57xx High Security EVM. This config is specific for the case of USB/UART booting. Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-02-09defconfigs: Add config for DRA7xx High Security EVM with USB Boot supportAndrew F. Davis2-0/+114
Add a new defconfig file for the DRA7xx High Security EVM. This config is specific for the case of USB booting. Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-02-09defconfigs: am57xx_hs_evm: Sync HS and non-HS defconfigsAndrew F. Davis1-0/+1
Additions have been made to the non-HS defconfig without the same being made to the HS defconfig, sync them. Signed-off-by: Andrew F. Davis <afd@ti.com>
2019-02-09defconfigs: dra7xx_hs_evm: Sync HS and non-HS defconfigsAndrew F. Davis1-1/+7
Additions have been made to the non-HS defconfig without the same being made to the HS defconfig, sync them. Signed-off-by: Andrew F. Davis <afd@ti.com>
2019-02-09bcm968580: enable watchdog and reboot with watchdogPhilippe Reynes1-0/+2
Enable watchdog and reboot with watchdog in the configuration. Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-02-09bcm968380gerg: enable watchdog and reboot with watchdogPhilippe Reynes1-0/+2
Enable watchdog and reboot with watchdog in the configuration. Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-02-09dt: bcm6858: add watchdogPhilippe Reynes1-0/+17
This commit add watchdog and sysreset watchdog in the bcm6858 device tree. Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-02-09dt: bcm6838: add watchdogPhilippe Reynes1-0/+17
This commit add watchdog and sysreset watchdog in the bcm6838 device tree. Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-02-09watchdog: bcm6345: allow to use this driver on arm bcm6858Philippe Reynes1-1/+1
This IP is also used on some arm SoC, so we allow to use it on arm bcm6858 too. Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-02-09watchdog: bcm6345: switch to raw I/O functionsPhilippe Reynes1-5/+5
This driver is used on several big endian mips board. So we could use raw I/O function instead of forcing big endian access. Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-02-09fdt: support booting with dtb in Android imageShawn Guo1-0/+21
Some platforms choose to store device tree blob in Android image second area. Let's try to look for dtb from there when booting an Android image, and use it for booting if found. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2019-02-08Prepare v2019.04-rc1Tom Rini1-2/+2
Signed-off-by: Tom Rini <trini@konsulko.com>
2019-02-07configs: Resync with savedefconfigTom Rini132-182/+142
Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
2019-02-07Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini147-2084/+4302
- SPI-NOR support
2019-02-07MAINTAINERS: Add an entry for SPI NORVignesh R1-1/+9
Add myself as co-maintainer for U-Boot SPI NOR subsystem. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jagan@openedev.com> [jagan: drop mtd/spi file from SPI entry] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-02-07configs: Don't use SPI_FLASH_BAR as defaultVignesh R91-90/+6
Now that new SPI NOR layer uses stateless 4 byte opcodes by default, don't enable SPI_FLASH_BAR. For SPI controllers that cannot support 4-byte addressing, (stm32_qspi.c, fsl_qspi.c, mtk_qspi.c, ich.c, renesas_rpc_spi.c) add an imply clause to enable SPI_FLASH_BAR so as to not break functionality. Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-07configs: Remove SF_DUAL_FLASHVignesh R17-108/+0
SF_DUAL_FLASH claims to enable support for SF_DUAL_STACKED_FLASH and SF_DUAL_PARALLEL_FLASH. But, in current U-Boot code, grepping for above enums yield no user and therefore support seems to be incomplete. Remove these configs so as to avoid confusion. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-07spl: Kconfig: Enable SPI_FLASH_TINY by default for SPLVignesh R1-0/+1
SPL only needs to be able to read from SPI Flash to load next stage and does not really need write/erase etc. Therefore in order to reduce SPI Flash code size in SPL, enable SPI_FLASH_TINY, that only supports reading from SPI flash, as default. Note: Since, SPI_FLASH_TINY does not support SPI_FLASH_BAR, SPI_FLASH_TINY is not enabled for boards with SPI controllers that cannot support 4 byte addressing. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-07mtd: spi: Add lightweight SPI flash stack for SPLVignesh R6-264/+1126
Add a tiny SPI flash stack that just supports reading data/images from SPI flash. This is useful for boards that have SPL size constraints and would need to use SPI flash framework just to read images/data from flash. There is approximately 1.5 to 2KB savings with this. Based on prior work of reducing spi flash id table by Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-07mtd: spi: Remove unused filesVignesh R2-1548/+0
spi_flash and spi_flash_ids are no longer needed after SPI NOR migration. Remove them. Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-07mtd: spi: Switch to new SPI NOR frameworkVignesh R9-365/+113
Switch spi_flash_* interfaces to call into new SPI NOR framework via MTD layer. Fix up sf_dataflash to work in legacy way. And update sandbox to use new interfaces/definitions Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-07mtd: spi: sf_probe: Add "jedec, spi-nor" compatible stringVignesh R1-0/+1
Linux uses "jedec,spi-nor" as compatible string for JEDEC compatible SPI Flash device nodes. Therefore make U-Boot also to look for the same compatible string so that we can use Linux DTS files as is. Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-07mtd: spi: spi-nor-core: Add back U-Boot specific featuresVignesh R2-3/+168
For legacy reasons, we will have to keep around U-Boot specific SPI_FLASH_BAR and SPI_TX_BYTE. Add them back to the new framework Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-07mtd: spi: spi-nor-core: Add SFDP supportVignesh R3-7/+649
Sync Serial Flash Discoverable Parameters (SFDP) parsing support from Linux. This allows auto detection and configuration of Flash parameters. Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-07mtd: spi: spi-nor-core: Add 4 Byte addressing supportVignesh R1-0/+141
Sync changes from Linux SPI NOR framework to add 4 byte addressing support. This is required in order to support flashes like MT35x that no longer support legacy Bank Address Register(BAR) way of accessing >16MB region. Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-07mtd: spi: spi-nor-core: Add SPI MEM supportVignesh R1-4/+93
Many SPI controllers have special MMIO interfaces which provide accelerated read/write access but require knowledge of flash parameters to make use of it. Recent spi-mem layer provides a way to support such controllers. Therefore, add spi-mem support to spi-nor-core as a way to support SPI controllers with MMIO interface. SPI MEM layer takes care of translating spi_mem_ops to spi_xfer()s in case of legacy SPI controllers. Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-07mtd: spi: Port SPI NOR framework from LinuxVignesh R3-0/+2158
Current U-Boot SPI NOR support (sf layer) is quite outdated as it does not support 4 byte addressing opcodes, SFDP table parsing and different types of quad mode enable sequences. Many newer flashes no longer support BANK registers used by sf layer to a access >16MB of flash address space. So, sync SPI NOR framework from Linux v4.19 that supports all the above features. Start with basic sync up that brings in basic framework subsequent commits will bring in more features. Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-07sh: bitops: add hweight*() macrosVignesh R1-0/+4
Add hweight*() macros required for moving to new SF layer Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2019-02-07spi: Add non DM version of SPI_MEMVignesh R3-2/+108
Add non DM version of SPI_MEM to support easy migration to new SPI NOR framework. This can be removed once DM_SPI conversion is complete. Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-07spi: spi-mem: Claim SPI bus before spi mem accessVignesh R1-5/+8
It is necessary to call spi_claim_bus() before starting any SPI transactions and this restriction would also apply when calling spi-mem operations. Therefore claim and release bus before requesting transfer via exec_op. Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-07spi: spi-mem: Extend spi_mem_adjust_op_size() to honor max xfer sizeVignesh R1-0/+19
Extend spi_mem_adjust_op_size() to take spi->max_write_size and spi->max_read_size into account. Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-07spi: spi-mem: Allow use of spi_mem_exec_op for all SPI modesVignesh R1-9/+0
SPI controllers support all types of SPI modes including dual/quad bus widths. Therefore remove constraint wrt SPI mode from spi-mem layer. Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-07bitops: Fix GENMASK definition for SandboxVignesh R1-0/+5
In arch/sandbox/include/asm/types.h we have Therefore for 32 bit Sandbox build BITS_PER_LONG turns out to be 32 as CONFIG_PHYS64 is not set This messes up the current logic of GENMASK macro due to mismatch b/w size of unsigned long (64 bit) and that of BITS_PER_LONG. Fix this by using CONFIG_SANDBOX_BITS_PER_LONG which is set to 64/32 based on the host machine on which its being compiled. Without this patch: GENMASK(14,0) => 0x7fffffffffff After this patch: GENMASK(14,0) => 0x7fff Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-02-07configs: Move CONFIG_SPI_FLASH into defconfigsVignesh R32-9/+24
Completely move CONFIG_SPI_FLASH from remaining board header files to defconfigs Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-06arm: dts: am33xx: introduce 'am33xx-u-boot.dtsi'Hannes Schmelzer1-0/+11
commit fdce9d35dc36 ("arm: dts: am33xx: Sync dts with Linux 4.20.0") did remove the "u-boot,dm-spl" flag from the 'ocp' bus which was introduced with commit 19aa4ac09db9 ("dts: am33xx: add u-boot, dm-spl to ocp bus") Due to this all boards having CONFIG_SPL_OF_CONTROL enabled are broken because they cannot bind/probe the boot-media interface during SPL stage. This commit introduces the 'am33xx-u-boot.dtsi' which is included with the auto include mechanism. The am33xx-u-boot-dtsi adds the important "u-boot,dm-pre-reloc" to the 'ocp bus' (the root bus of almost all peripherals, at least the bootable ones). The peripherials (mmc, spi, ...) needed during SPL stage need to be equipped with the 'u-boot,dm-pre-reloc' in their responsible dts file. Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
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