summaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
2023-03-08riscv: dts: enable hdmi dts config in ubootkeith.zhao2-46/+13
hdmi can show a bitmap logo while uboot start and the default resolution is 1920x1080@60fps Signed-off-by: keith.zhao<keith.zhao@statfivetech.com>
2023-02-28Merge branch 'CR_3696_adjust_cpu_vol_mason.huo' into 'jh7110-master'andy.hu2-0/+62
CR_3696: Add cpu voltage set commands See merge request sdk/u-boot!37
2023-02-28board: starfive: jh7110: Add cpu voltage set commandsmason.huo2-0/+62
Get the binning information from OTP, and set change the cpu max voltage accordingly. Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
2023-02-24Merge branch 'CR_3504_enable_sbi_command_michael.zhu' into 'jh7110-master'andy.hu1-0/+1
CR_3504: Enable sbi command in U-Boot See merge request sdk/u-boot!36
2023-02-24Merge branch 'CR_3455_PCIe_support_mason.huo' into 'jh7110-master'andy.hu10-12/+690
CR_3455 pci: Add Starfive JH7110 pcie driver See merge request sdk/u-boot!33
2023-02-22i2c: designware_i2c: Add ACPI configure limitationMason Huo1-0/+2
As the i2c_designware_pci.c uses ACPI APIs, add the ACPI table generation configuration for its compilation. Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
2023-02-22net: rtl8169: Add one more device IDMason Huo1-0/+3
Add the NIC device ID and adjust the bar regions. Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
2023-02-22riscv: dts: starfive: Enable PCIe host controllerMason Huo2-12/+114
Enable and add pinctrl configuration for PCIe host controller. Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
2023-02-22configs: starfive-jh7110: Add support for PCIe host driverMason Huo1-0/+6
Add the PCIe host driver config, also add the rtl8169 & nvme driver support. Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
2023-02-22clk: starfive: Add PCIe clocks for PCIe controllerMason Huo1-0/+43
Add the stg clocks for PCIe controller. Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
2023-02-22pci: Add Starfive JH7110 pcie driverMason Huo4-0/+522
Port the JH7110 pcie host driver from linux kernel. Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
2023-02-21Enable sbi command in U-BootMichaelZhuxx1-0/+1
Signed-off-by: MichaelZhuxx <michael.zhu@starfivetech.com>
2023-02-21Merge branch 'CR_3537_evb_515_uboot_compatibility_EVB_VF2_keith.zhao' into ↵andy.hu1-1/+1
'jh7110-master' CR#3537 riscv:uboot:cache driver See merge request sdk/u-boot!35
2023-02-21riscv:uboot:cache driverkeith.zhao1-1/+1
cache driver enabled by config STARFIVE_JH7110_L2CC_FLUSH if not , there is a dump on vf2 Signed-off-by:keith.zhao<keith.zhao@statfivetech.com>
2023-02-17Merge branch 'CR_3345_evb_515_uboot_mipi_logo_keith.zhao' into 'jh7110-master'andy.hu1-1/+1
display : uboot logo display See merge request sdk/u-boot!34
2023-02-17display : uboot logo displaykeith.zhao1-1/+1
replace the logo bmp for uboot logo display Signed-off-by:keith.zhao<keith.zhao@statfivetech.com>
2023-02-17Merge branch 'CR_3345_evb_515_uboot_mipi_logo_keith.zhao' into 'jh7110-master'andy.hu39-102/+4410
CR_3345: riscv:uboot:add cache driver See merge request sdk/u-boot!32
2023-02-17defconfig:riscv:jh7110: add mipi configkeith.zhao1-0/+25
add the new configs needed by mipi display Signed-off-by:keith.zhao<keith.zhao@statfivetech.com>
2023-02-17dts:riscv:jh7110: add mipi driver nodekeith.zhao2-94/+329
update dts node to support vout mipi driver Signed-off-by:keith.zhao<keith.zhao@statfivetech.com>
2023-02-17board:riscv:jh7110: modify config for starfive JH7110 boardkeith.zhao3-1/+23
add board_late_init to init display memory config the bitmap picture Signed-off-by:keith.zhao<keith.zhao@statfivetech.com>
2023-02-17vout:dc8200: add vout mipi driverkeith.zhao18-2/+3480
add vout mipi pipeline driver in uboot Signed-off-by:keith.zhao<keith.zhao@statfivetech.com>
2023-02-17i2c:desigware-snps: add i2c clock configkeith.zhao3-5/+28
add clock config for i2c2 and i2c5 update the i2c driver clock config Signed-off-by:keith.zhao<keith.zhao@statfivetech.com>
2023-02-17power: add power subsystem driver in ubootkeith.zhao9-0/+459
add power subsystem in driver,include pmu pmic and regulator pmu : dc8200 power pmic : mipi power regulator : entend power Signed-off-by:keith.zhao<keith.zhao@statfivetech.com>
2023-02-17riscv:cache:jh7110: add cache driverkeith.zhao3-0/+66
support flush_dcache_range interface STARFIVE_JH7110_L2CC_FLUSH Signed-off-by:keith.zhao<keith.zhao@statfivetech.com>
2023-02-03Merge branch 'CR_3238_Reserved_memory_mason.huo' into 'jh7110-master'andy.hu1-1/+11
CR_3238 exclude opensbi memory range in device tree See merge request sdk/u-boot!27
2023-02-03Merge branch 'CR_1432_add_sbi_reset_patch_minda' into 'jh7110-master'andy.hu7-3/+127
CR_1432 riscv: add missing SBI extension definitions See merge request sdk/u-boot!26
2023-02-03exclude opensbi memory range in device treeFelix Moessbauer1-1/+11
This patch explicitly excludes the memory range of the OpenSBI in the built-in device tree. When booting EFI, the efi loader has to know about that zone before loading the device tree for Linux, otherwise it tries to access 0x40000000, leading to an access violation. Signed-off-by: Felix Moessbauer <felix.moessbauer@siemens.com>
2023-02-02sysreset: provide SBI based sysreset driverHeinrich Schuchardt7-1/+90
Provide sysreset driver using the SBI system reset extension. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Samuel Holland <samuel@sholland.org>
2023-02-02riscv: add missing SBI extension definitionsHeinrich Schuchardt1-2/+37
Add the System Reset Extension and the Hart State Management Extension definitions. Add missing RFENCE Extension enum values. The SBI 0.1 extension constants are needed for the sbi command. Remove an #ifdef. Cf. https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.adoc Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-01-11Merge branch 'CR_3068_DEFCONFIG_yanhong.wang' into 'jh7110-master'andy.hu1-5/+5
CR 3068 configs: starfive-jh7110: update the value of CONFIG_SYS_MALLOC_F_LEN See merge request sdk/u-boot!25
2023-01-11Merge branch 'CR_3067_add_boot_hard_id_minda' into 'jh7110-master'andy.hu1-0/+1
CR_3067 dts: add boot-hart-id property in dts See merge request sdk/u-boot!24
2023-01-11configs: starfive-jh7110: update the value of CONFIG_SYS_MALLOC_F_LENYanhong Wang1-5/+5
Update the value of CONFIG_SYS_MALLOC_F_LEN from 0x8000 to 0x10000. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
2023-01-09dts: add boot-hart-id property in dtsminda.chen1-0/+1
boot-hart-id is used by opensbi. Signed-off-by: minda.chen <minda.chen@starfivetech.com>
2023-01-06Merge branch 'CR_3049_Hibernation_mason.huo' into 'jh7110-master'andy.hu2-0/+20
CR_3049 dts: add i2c5 and attach pmic configuration See merge request sdk/u-boot!22
2023-01-06Merge branch 'CR_3006_OTP_yanhong.wang' into 'jh7110-master'andy.hu3-5/+14
CR_3006 misc: OTP: Starfive-jh7110: update the return value of starfive_otp_read See merge request sdk/u-boot!21
2023-01-06Merge branch 'CR_2708_VOUTCLK_yanhong.wang' into 'jh7110-master'andy.hu4-265/+490
CR 2708 clk:starfive: Add vout clock driver for StarFive JH7110 See merge request sdk/u-boot!23
2023-01-06Merge branch 'CR_2828_perf_support_minda' into 'jh7110-master'andy.hu1-0/+46
CR_2828 dts: pmu : add riscv pmu dts config See merge request sdk/u-boot!20
2023-01-05clk:starfive: Add vout clock driver for StarFive JH7110Yanhong Wang4-265/+490
Add vout clock driver for StarFive JH7110 Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
2023-01-05dts: add i2c5 and attach pmic configurationminda.chen2-0/+20
i2c5 and pmic is used by opensbi power management ops. Signed-off-by: minda.chen <minda.chen@starfivetech.com>
2023-01-03dts: pmu : add riscv pmu dts configminda.chen1-0/+46
add 7110 performance monitor for perf use Signed-off-by: minda.chen <minda.chen@starfivetech.com>
2023-01-03misc: OTP: Starfive-jh7110: update the return value of starfive_otp_readYanhong Wang3-5/+14
Update the return value to match the function prototype definition. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
2022-12-19Merge branch 'CR_2876_SET_CPU_FREQ_samin.guo' into 'jh7110-master'andy.hu2-3/+3
CR_2876: board:starfive:evb: Set the CPU default frequency to 1.0GHz See merge request sdk/u-boot!19
2022-12-16board:starfive:jh7110: Set the CPU default frequency to 1000MHzSamin Guo1-2/+2
Set to 1000M to ensure the CPU can work normally under 0.8V` voltage Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2022-12-14board:starfive:jh7110: default cpufreq is 1000Mhz.Samin Guo1-1/+1
The frequency of pll0 is set to 1000Mhz in the bootrom Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2022-11-25Merge branch 'CR_2709_pinctrl_jianlong' into 'jh7110-master'andy.hu13-28/+1518
CR_2709 dt-bindings: pinctrl: Add StarFive JH7110 pinctrl definitions See merge request sdk/u-boot!18
2022-11-23board:starfive:Remove usb/sdio0/sdio1 gpio initJianlong Huang1-21/+0
Remove usb/sdio0/sdio1 gpio init. Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
2022-11-23dts:starfive:Add pinctrl configJianlong Huang2-7/+59
Add pinctrl config about usb/sdio0 Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
2022-11-21configs: Enable STARFIVE_PINCTRLJianlong Huang1-0/+4
Enable STARFIVE_PINCTRL and PINCTRL_FULL Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
2022-11-21pinctrl: starfive: Add StarFive JH7110 driverKuan Lim Lee8-0/+1028
Add pinctrl driver for StarFive JH7110 SoC. Signed-off-by: Kuan Lim Lee <kuanlim.lee@linux.starfivetech.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
2022-11-21dt-bindings: pinctrl: Add StarFive JH7110 pinctrl definitionsJianlong Huang1-0/+427
Add pinctrl definitions for StarFive JH7110 SoC. Signed-off-by: Kuan Lim Lee <kuanlim.lee@linux.starfivetech.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
generated by cgit v1.2.3 (git 2.39.0) at 2024-08-05 03:16:52 +0300