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2023-05-31imx: fix header inclusion guardsAndre Przywara1-1/+1
It seems like the header inclusion guards for some IMX related headers were misspelled or got out of sync. Make the preprocessor symbols for the #ifndef and #define lines the same, so that the double inclusion protection works as expected. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2023-03-29imx: ahab: Move imx9 and imx8ulp AHAB support togetherYe Li1-0/+2
Use common file ele_ahab.c for i.MX9 and iMX8ULP AHAB support, since both of them use same sentinel ELE APIs Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-03-29imx: imx8ulp: Configure XRDC PDAC and MSC for DBD owner=S400 onlyYe Li1-0/+1
This patch is used to support DBD owner fuse changed to S400 only. The XRDC PDAC2 for LPAV pbridge5 and MSC1/2/3 for GPIO and LPAV are not configured by S400 default setting. So these PDAC and MSC are invalid, only DBD owner can access the corresponding resources. We have to configure necessary PDAC and MSC for SPL before DDR initialization. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-03-29imx: imx8ulp: Adjust handshake to sync TRDC and XRDC completionYe Li1-0/+1
To fit the DBD_EN fused part, we re-design the TRDC and XRDC assignment. M33 will be the TRDC owner and needs to configure TRDC. A35 is the XRDC owner, ATF will configure XRDC. The handshake between U-boot and M33 image is used to sync TRDC and XRDC configuration completion. Once the handshake is done, A35 and M33 can access the allowed resources in others domain. The handshake is needed when M33 is booted or DBD_EN fused, because both cases will enable the TRDC. If handshake is timeout, the boot will hang. We use SIM GPR0 to pass the info from SPL to u-boot, because before the handshake, u-boot can't access SEC SIM and FSB. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com>
2023-03-29imx: imx8ulp: Get chip revision from SentinelYe Li2-0/+2
In both SPL and u-boot, after probing the S400 MU, get the chip revision, lifecycle and UID from Sentinel. Update get_cpu_rev to use the chip revision not hard coded it for A0 Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2022-07-26misc: imx: S400_API: Move S400 MU and API to a common placeYe Li2-58/+0
Since iMX9 uses S401 which shares the API with iMX8ULP. So move S400 MU driver and API to a common place and selected by CONFIG_IMX_SENTINEL Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26imx: imx9: support romapiPeng Fan1-4/+0
i.MX9 shares same ROM API with i.MX8ULP, so make the i.MX8ULP the function prototype common and usable by i.MX9. Also include mmc env functions that use ROM API. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26imx: move get_boot_device to common headerPeng Fan1-1/+0
Most i.MX implements get_boot_device, move it to common header to simplify code Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-05-20i.MX8ULP: add display_ele_fw_version apiGaurav Jain1-0/+2
implement get f/w version api. print ele f/w version in spl. Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Pankaj Gupta <pankaj.gupta@nxp.com>
2022-04-12misc: S400_API: Update S400 API for buffer dumpYe Li1-1/+2
Add ahab_dump_buffer API to dump AHAB buffer for debug purpose Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-04-12misc: S400_API: add ahab_release_caamClement Faure1-0/+2
Add ahab_release_caam() function to the S400 API. Signed-off-by: Clement Faure <clement.faure@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-04-12imx: imx8ulp_evk: Skip init DDR for reboot in dual boot modeYe Li1-1/+1
When M33 is LPAV owner in dual boot, DDR, PCC5, CGC2 won't be reset during APD reset. So no need to init DDR again after reboot, but need to reconfigure the PLL4 PFD/PFDDIV/LPAV NIC etc, because kernel may change or disable some of them. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-04-12imx: imx8ulp: add ND/LD clockPeng Fan2-4/+7
Add a new ddr script, defconfig for ND Configure the clock for ND mode changing A35 to 960MHz for OD mode Update NIC CLK for the various modes Introduce clock_init_early/late, late is used after pmic voltage setting, early is used in the very early stage for upower mu, lpuart and etc. Note: NIC runs at 324MHz, 442MHz has some random kernel hang issue with cpuidle enabled now. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-04-12imx: imx8ulp: add CAAM clock entryPeng Fan1-0/+1
Add CAAM clock entry in PCC3 Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-04-12imx: imx8ulp: Add M33 handshake functionsYe Li2-0/+3
Add functions to check if M33 image is booted and handshake with M33 image via MU. A core notifies M33 to start init by FCR F0, then wait M33 init done signal by checking FSR F0. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Biwen Li <biwen.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-04-12imx: imx8ulp: include pcc/cgc header in clock headerPeng Fan1-0/+3
With this change, we no need to include pcc/cgc header files both. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05imx8ulp: clock: Handle the DDRLOCKED when setting DDR clockYe Li1-0/+1
The DDRLOCKED bit in CGC2 DDRCLK will auto lock up and down by HW according to DDR DIV updating or DDR CLK halt status change. So DDR PCC disable/enable will trigger the lock up/down flow. We need wait until unlock to ensure clock is ready. And before configuring the DDRCLK DIV, we need polling the DDRLOCKED until it is unlocked. Otherwise writing ti DIV bits will not set. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05imx8ulp: clock: Support to enable/disable the ADC1 clockAlice Guo4-0/+10
This patch implements enable_adc1_clk() to enable or disable the ADC1 clock on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Alice Guo <alice.guo@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05imx8ulp: clock: Support to reset DCNano and MIPI DSIYe Li1-0/+1
When LPAV is allocated to RTD, the LPAV won't be reset. So we have to reset DCNano and MIPI DSI in u-boot before enabling the drivers Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05imx8ulp: Workaround LPOSC_TRIM fuse load issueYe Li1-0/+1
8ULP ROM should read the LPOSC trim BIAS fuse to fill the CGC0 LPOSCCTRL[7:0], but it writes a fixed value on A0.1 revision. A0.2 will fix the issue in ROM. But A0.1 we have to workaround it in SPL by setting LPOSCCTRL BIASCURRENT again. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05imx8ulp: Fix DCNANO QoS settingYe Li1-0/+1
The setting does not have effect because we should set it after power on the PS16 for NIC AV. So move it after upower_init which has powered on all PS Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05imx8ulp_evk: Control LPI2C0 PCA6416 and TPM0 for displayYe Li1-0/+4
The board use IO9 of PCA6416 on LPI2C0 and TPM0 for MIPI DSI MUX and backlight. However the LPI2C0 and TPM0 are M33 resources, in this patch we simply access them, but this is a temporary solution. We will modify it when M33 FW changes to set MIPI DSI panel as default path and enable backlight after reset. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05imx8ulp: clock: Add MIPI DSI clock and DCNano clockYe Li1-0/+2
Add the DSI clock enable and disable with PCC reset used. Add the LCD pixel clock calculation and configuration for DCNano Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05imx8ulp: clock: Support LPAV clocks in cgc and pccYe Li2-5/+93
Add the PCC5 clocks support and more LPAV clocks and PLL4 PFD in CGC. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09imx8ulp: add upower api supportPeng Fan1-0/+15
Add upower api support, this is modified from upower firmware exported package. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09imx8ulp: move struct mu_type to common headerPeng Fan1-0/+25
Move struct mu_type to common header to make it reusable by upower and S400 Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09arm: imx8ulp: add iomuxc supportPeng Fan1-0/+82
Add i.MX8ULP iomuxc support Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09arm: iMX8ULP: Add boot device relevant functionsYe Li1-0/+1
Read from ROM API to get current boot device. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09imx8ulp: unify rdc functionsPeng Fan1-0/+27
Unify rdc function to rdc.c Update soc.c to use new rdc function Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09arm: imx8ulp: add rdc supportPeng Fan1-0/+2
There is xrdc inside i.MX8ULP, we need to configure permission to make sure AP non-secure world could access the resources. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09arm: imx8ulp: release and configure XRDC at early phaseYe Li1-0/+12
Since S400 will set the memory of SPL image to R/X. We can't write to any data in SPL image. 1. Set the parameters save/restore only for u-boot, not for SPL. to avoid write data. 2. Not use MU DM driver but directly call MU API to send release XRDC to S400 at early phase. 3. Configure the SPL image memory of SRAM2 to writable (R/W/X) Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09drivers: misc: s400_api: Update API for fuse read and writeYe Li1-1/+6
Add API to support fuse read and write Signed-off-by: Ye Li <ye.li@nxp.com>
2021-08-09drivers: misc: imx8ulp: Update S400 API for release RDCYe Li1-1/+1
The RDC API is updated to add a field for XRDC or TRDC Signed-off-by: Ye Li <ye.li@nxp.com>
2021-08-09drivers: misc: imx8ulp: Add S400 API for image authenticationYe Li1-1/+7
Add S400 API for image authentication Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09arm: imx8ulp: add clock supportPeng Fan4-1/+278
Add i.MX8ULP clock support Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09driver: misc: Add MU and S400 API to communicate with SentinelYe Li1-0/+30
Add MU driver and S400 API. Need enable MISC driver to work Signed-off-by: Ye Li <ye.li@nxp.com>
2021-08-09arm: imx8ulp: add container supportYe Li1-0/+2
i.MX8ULP support using ROM API to load container image, it use same ROM API as i.MX8MN/MP, and use same container format as i.MX8QM/QXP. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09arm: imx: basic i.MX8ULP supportPeng Fan5-0/+288
Add basic i.MX8ULP support For the MMU part, Using a simple way the calculate the MMU size to avoid default heavy calcaulation. And align address and size in the table settings to 2MB or 4GB as much as possible. So we can reduce the 4K page allocations in MMU table which will spends much time in create the page table Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09arm: imx8ulp: support print cpu infoPeng Fan1-0/+3
Support print cpu info. the clock function has not been added, it will be added in following patches. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09arm: imx: add i.MX8ULP cpu type and helperPeng Fan1-0/+11
Add i.MX8ULP cpu type and helpers. Signed-off-by: Peng Fan <peng.fan@nxp.com>
generated by cgit v1.2.3 (git 2.39.0) at 2024-09-07 04:33:20 +0300