starfive-tech/u-boot.git - StarFive Tech U-Boot for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2020-09-03	arm: socfpga: soc64: Check FPGA Config status register before bridge reset	Chee Hong Ang	3	-9/+20
2020-07-01	socfpga: Mark socfpga_fpga_add() as static inline in the non-FPGA case	Tom Rini	1	-1/+1
2020-06-26	arm: socfpga: misc_s10: Fix EMAC register address calculation	Ley Foon Tan	1	-1/+1
2020-05-19	common: Drop linux/bitops.h from common header	Simon Glass	14	-0/+19
2020-05-19	Use __ASSEMBLY__ as the assembly macros	Simon Glass	4	-6/+6
2020-05-19	common: Drop linux/delay.h from common header	Simon Glass	3	-0/+3
2020-05-19	common: Drop log.h from common header	Simon Glass	6	-0/+6
2020-05-19	command: Remove the cmd_tbl_t typedef	Simon Glass	2	-2/+6
2020-05-19	common: Drop init.h from common header	Simon Glass	12	-0/+12
2020-05-19	common: Drop net.h from common header	Simon Glass	1	-0/+1
2020-04-27	arm: socfpga: stratix10: Fix incorrect CLKMGR_S10_PERPLL_BYPASS offset	Ley Foon Tan	1	-1/+1
2020-04-22	spl: mmc: Rename spl_boot_mode() to spl_mmc_boot_mode()	Harald Seiler	4	-4/+4
2020-04-13	arm: socfpga: arria10: Enable cache driver in SPL	Ley Foon Tan	1	-0/+1
2020-03-31	arm: socfpga: arria10: Add save_boot_params()	Ley Foon Tan	1	-0/+32
2020-03-31	arm: socfpga: Add onchip RAM size macro	Ley Foon Tan	2	-0/+4
2020-03-04	ARM: socfpga: Add initial support for the ABB SECU board	Holger Brunck	1	-0/+10
2020-02-11	Merge tag 'dm-pull-6feb20' of https://gitlab.denx.de/u-boot/custodians/u-boot-dm	Tom Rini	2	-0/+2
2020-02-06	dm: core: Create a new header file for 'compat' features	Simon Glass	2	-0/+2
2020-02-05	ddr: altera: Add DDR2 support to Gen5 driver	Marek Vasut	3	-32/+80
2020-02-03	ARM: socfpga: Drop last use of socfpga_reset_manager	Marek Vasut	1	-4/+1
2020-01-18	common: Move hang() to the same header as panic()	Simon Glass	6	-0/+6
2020-01-17	common: Move reset_cpu() to the CPU header	Simon Glass	1	-0/+1
2020-01-07	arm: socfpga: stratix10: Enable SMMU access	Thor Thayer	1	-0/+7
2020-01-07	arm: socfpga: agilex: Enable Agilex SoC build	Ley Foon Tan	2	-0/+25
2020-01-07	arm: socfpga: agilex: Add SPL for Agilex SoC	Ley Foon Tan	2	-0/+101
2020-01-07	arm: agilex: Add clock handoff offset for Agilex	Ley Foon Tan	2	-4/+10
2020-01-07	arm: socfpga: agilex: Add clock wrapper functions	Ley Foon Tan	4	-0/+105
2020-01-07	clk: agilex: Add clock driver for Agilex	Ley Foon Tan	1	-0/+5
2020-01-07	arm: socfpga: Fix CLKMGR_INTOSC_HZ to 400MHz	Ley Foon Tan	1	-3/+1
2020-01-07	arm: socfpga: Move Stratix10 and Agilex clock manager common code	Ley Foon Tan	2	-13/+26
2020-01-07	arm: socfpga: agilex: Add system manager support	Ley Foon Tan	1	-1/+2
2020-01-07	arm: socfpga: Move Stratix10 and Agilex system manager common code	Ley Foon Tan	11	-155/+158
2020-01-07	arm: socfpga: agilex: Add reset manager support	Ley Foon Tan	1	-1/+2
2020-01-07	arm: socfpga: Move Stratix10 and Agilex reset manager common code	Ley Foon Tan	4	-106/+49
2020-01-07	arm: socfpga: Move firewall code to firewall file	Ley Foon Tan	4	-95/+116
2020-01-07	arm: socfpga: agilex: Add base address for Intel Agilex SoC	Ley Foon Tan	1	-0/+4
2020-01-07	arm: socfpga: Convert clock manager from struct to defines	Ley Foon Tan	9	-468/+497
2020-01-07	arm: socfpga: Convert system manager from struct to defines	Ley Foon Tan	20	-400/+254
2020-01-07	arm: socfpga: Convert reset manager from struct to defines	Ley Foon Tan	13	-149/+150
2019-12-03	common: Move some cache and MMU functions out of common.h	Simon Glass	2	-0/+2
2019-12-03	common: Move get_ticks() function out of common.h	Simon Glass	1	-0/+1
2019-11-25	ARM: socfpga: Unreset NAND in SPL on Gen5	Marek Vasut	1	-0/+7
2019-11-25	ARM: socfpga: Add ArriaV ST/SX ID	Marek Vasut	1	-0/+2
2019-11-25	ARM: socfpga: Purge pending transactions upon enabling bridges on Gen5	Marek Vasut	1	-0/+3
2019-11-25	ARM: socfpga: Actually put bridges into reset on Gen5 in bridge disable	Marek Vasut	1	-1/+1
2019-11-21	socfpga: fix include guard in misc.h (arch vs. global)	Simon Goldschmidt	1	-3/+3
2019-11-08	arm: socfpga: gen5: fix ERR_PTR_OFFSET	Simon Goldschmidt	1	-0/+3
2019-10-09	ARM: socfpga: vining_fpga: Rename VINING\|FPGA	Marek Vasut	1	-5/+5
2019-10-08	spl: Convert CONFIG_SPL_SIZE_LIMIT to hex	Simon Glass	1	-1/+1
2019-10-08	spl: Allow tiny printf() to be controlled in SPL and TPL	Simon Glass	1	-2/+2