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starfive-tech/u-boot.git
Fedora_JH7100_2021.04
Fedora_JH7100_2021.07
Fedora_JH7100_upstream
Fedora_JH7100_upstream_devel
JH7100_Multimedia_V0.1.0
JH7100_VisionFive_OH_dev
JH7100_VisionFive_devel
JH7100_starlight_multimedia
JH7100_upstream
JH7100_upstream_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_devel-v3.9.3
dubhe_fpga_dev_v2023.10
master
rtthread_AMP
visionfive_devel
StarFive Tech U-Boot for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
root
/
arch
/
arm
/
mach-tegra
/
tegra124
/
clock.c
Age
Commit message (
Expand
)
Author
Files
Lines
2020-05-19
common: Drop linux/delay.h from common header
Simon Glass
1
-0
/
+1
2020-05-19
common: Drop log.h from common header
Simon Glass
1
-0
/
+1
2020-05-19
common: Drop init.h from common header
Simon Glass
1
-0
/
+1
2019-05-24
tegra: Correct tegra124 clock name
Simon Glass
1
-1
/
+1
2018-05-07
SPDX: Convert all of our single license tags to Linux Kernel style
Tom Rini
1
-2
/
+1
2017-06-09
tegra: Init clocks even when SPL did not run
Simon Glass
1
-0
/
+18
2016-09-27
ARM: tegra: add APIs the clock uclass driver will need
Stephen Warren
1
-16
/
+48
2016-09-27
ARM: tegra: add peripheral clock init table
Stephen Warren
1
-0
/
+23
2015-09-17
ARM: tegra124: Clear IDDQ when enabling PLLC
Thierry Reding
1
-0
/
+5
2015-09-17
ARM: tegra: clk_m is the architected timer source clock
Thierry Reding
1
-2
/
+2
2015-08-18
of: clean up OF_CONTROL ifdef conditionals
Masahiro Yamada
1
-2
/
+2
2015-08-13
tegra: Correct logic for reading pll_misc in clock_start_pll()
Simon Glass
1
-1
/
+3
2015-08-06
Tegra: PLL: use per-SoC pllinfo table instead of PLL_DIVM/N/P, etc.
Tom Warren
1
-4
/
+40
2015-06-09
tegra: Add missing tegra124 peripherals
Simon Glass
1
-1
/
+1
2015-05-13
tegra124: clock: Add display clocks and functions
Simon Glass
1
-5
/
+136
2015-02-21
ARM: tegra: collect SoC sources into mach-tegra
Masahiro Yamada
1
-0
/
+935