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Fedora_JH7100_2021.07
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Fedora_JH7100_upstream_devel
JH7100_Multimedia_V0.1.0
JH7100_VisionFive_OH_dev
JH7100_VisionFive_devel
JH7100_starlight_multimedia
JH7100_upstream
JH7100_upstream_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_devel-v3.9.3
dubhe_fpga_dev_v2023.10
master
rtthread_AMP
visionfive_devel
StarFive Tech U-Boot for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
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arch
/
mips
/
include
/
asm
/
mipsregs.h
Age
Commit message (
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Author
Files
Lines
2020-07-18
mips: sync asm/mipsregs.h with Linux 5.7
Daniel Schwierzeck
1
-194
/
+1008
2020-07-18
mips: traps: Set WG bit in EBase register on Octeon
Stefan Roese
1
-0
/
+1
2020-05-19
common: Drop linux/bitops.h from common header
Simon Glass
1
-0
/
+1
2018-12-19
MIPS: move create_tlb() in an proper header: mipsregs.h
Gregory CLEMENT
1
-0
/
+11
2018-12-19
MIPS: remove local_irq_[save|restore] from CP0 macros
Daniel Schwierzeck
1
-7
/
+0
2018-05-07
SPDX: Convert all of our single license tags to Linux Kernel style
Tom Rini
1
-2
/
+1
2016-11-30
MIPS: fix iand optimize setup of CP0 registers
Daniel Schwierzeck
1
-0
/
+1
2016-09-21
MIPS: Hang if run on a secondary CPU
Paul Burton
1
-0
/
+7
2016-09-21
MIPS: L2 cache support
Paul Burton
1
-0
/
+5
2016-09-21
MIPS: Preserve Config implementation-defined bits
Paul Burton
1
-0
/
+1
2016-01-16
MIPS: sync processor and register definitions with linux-4.4
Daniel Schwierzeck
1
-434
/
+1061
2015-08-21
mips: Use unsigned int when reading c0 registers
Chris Packham
1
-2
/
+2
2013-11-09
mips32: detect L1 cache sizes if they're not defined
Paul Burton
1
-0
/
+6
2010-04-13
Move architecture-specific includes to arch/$ARCH/include/asm
Peter Tyser
1
-0
/
+1364