starfive-tech/u-boot.git - StarFive Tech U-Boot for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2018-09-22	MIPS: cache: remove config option CONFIG_SYS_MIPS_CACHE_MODE	Daniel Schwierzeck	1	-5/+1
2018-09-22	MIPS: cache: make index base address configurable	Daniel Schwierzeck	1	-10/+8
2018-09-22	MIPS: cache: optimise changing of k0 CCA mode	Daniel Schwierzeck	1	-22/+32
2018-09-22	MIPS: cache: reimplement dcache_[status, enable, disable]	Daniel Schwierzeck	1	-46/+0
2018-05-07	SPDX: Convert all of our single license tags to Linux Kernel style	Tom Rini	1	-2/+1
2016-09-21	MIPS: Ensure cache ops complete in mips_cache_reset	Paul Burton	1	-0/+2
2016-09-21	MIPS: Clear hazard between TagLo writes & cache ops	Paul Burton	1	-0/+1
2016-09-21	MIPS: Join the coherent domain when a CM is present	Paul Burton	1	-0/+38
2016-09-21	MIPS: L2 cache support	Paul Burton	1	-5/+178
2016-09-21	MIPS: Define register names for cache init	Paul Burton	1	-19/+23
2016-09-21	MIPS: Enable use of the instruction cache earlier	Paul Burton	1	-0/+13
2016-05-31	MIPS: Split I & D cache line size config	Paul Burton	1	-2/+2
2016-05-31	MIPS: Move cache sizes to Kconfig	Paul Burton	1	-3/+3
2016-05-21	MIPS: Use unchecked immediate addition/subtraction	Paul Burton	1	-1/+1
2016-01-16	MIPS: sync processor and register definitions with linux-4.4	Daniel Schwierzeck	1	-8/+8
2015-01-29	MIPS: clear TagLo select 2 during cache init	Paul Burton	1	-2/+8
2015-01-29	MIPS: allow systems to skip loads during cache init	Paul Burton	1	-6/+13
2015-01-29	MIPS: inline mips_init_[id]cache functions	Paul Burton	1	-58/+28
2015-01-29	MIPS: refactor cache loops to a macro	Paul Burton	1	-17/+13
2015-01-29	MIPS: refactor L1 cache config reads to a macro	Paul Burton	1	-56/+41
2015-01-29	MIPS: unify cache initialization code	Paul Burton	1	-0/+277