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2021-01-24mips: mtmips: add two reference boards for mt7620Weijie Gao4-0/+216
The mt7620_rfb board supports integrated 10/100M PHYs plus two external giga PHYs. It also has 8MB SPI-NOR, mini PCI-e x1 slot, SDHC and USB. The mt7620_mt7530_rfb boards supports an external MT7530 giga switch and a 16MB SPI-NOR flash. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2021-01-24mips: mtmips: add support for MediaTek MT7620 SoCWeijie Gao13-0/+1117
This patch adds support for MediaTek MT7620 SoC. All files are dedicated for u-boot. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2021-01-24mips: mtmips: add support to initialize SDRAMWeijie Gao2-0/+63
This patch adds support for mtmips SoCs to initialize the SDRAM. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2021-01-24mips: enable _machine_restart for splWeijie Gao1-1/+1
The sysreset driver has a config CONFIG_SPL_SYSRESET for the spl stage. Change CONFIG_SYSRESET to CONFIG_IS_ENABLED(SYSRESET) will give spl a chance to use _machine_restart instead of the sysreset driver. Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2021-01-24mips: mtmips: fix dram size detection in dram_initWeijie Gao1-3/+2
CONFIG_SYS_SDRAM_BASE points to cached memory, i.e. KSEG0, which is not suitable for detecting memory size. Replace CONFIG_SYS_SDRAM_BASE with KSEG1, and make dram_init() always do memory size detection in any stage. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2021-01-24mips: mtmips: select SYSRESET for mt7628 onlyWeijie Gao2-1/+1
Currently only mt7628 needs the sysreset driver, do not select it for mt7620. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2021-01-24mips: mtmips: move mt7628 related Kconfig into mt7628 subdirectoryWeijie Gao2-52/+54
This patch is a preparation for add a new soc fot mtmips. Move all mt7628 related Kconfig (boards and UART selection) into mt7628 subdirectory and make sure the top directory of mtmips contains only selection for SoCs. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2021-01-24mips: dts: switch to board defines for dtb for mtmipsWeijie Gao1-3/+2
Previous the dts files for gardena-smart-gateway-mt7688 and linkit-smart-7688 are set to be built when mtmips is selected. This can lead to a compilation error if another soc is added to this arch with different dtsi files. So it's better to build the dtb only if their board is selected. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2021-01-15common: board_r: Drop arch-specific ifdefs around initr_trapOvidiu Panait1-1/+8
In order to remove the arch-specific ifdefs around initr_trap, introduce arch_initr_trap weak initcall. Implementations for ppc/m68k/mips have been moved to arch/<arch>/lib/traps.c Default implementation is a nop stub. Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2021-01-06Merge tag 'dm-pull-5jan21' of git://git.denx.de/u-boot-dm into nextTom Rini1-1/+1
Driver model: make some udevice fields private Driver model: Rename U_BOOT_DEVICE et al. dtoc: Tidy up and add more tests ns16550 code clean-up x86 and sandbox minor fixes for of-platdata dtoc prepration for adding build-time instantiation
2021-01-05dm: Rename DM_GET_DRIVER() to DM_DRIVER_GET()Simon Glass1-1/+1
In the spirit of using the same base name for all of these related macros, rename this to have the operation at the end. This is not widely used so the impact is fairly small. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-18spi: dw: Add SoC-specific compatible stringsSean Anderson2-2/+2
This adds SoC-specific compatible strings to all users of the designware spi device. This will allow for the correct driver to be selected for each device. Where it is publicly documented, a compatible string for the specific device version has also been added. Devices without publicly-documented device versions include MSCC SoCs, and Arc Socs. All compatible strings except those for SoCFPGAs and some of the versioned strings have been taken from Linux. Since SSI_MAX_XFER_SIZE is determined at runtime, this is not strictly necessary. However, it is a good cleanup and brings things closer to Linux. Signed-off-by: Sean Anderson <seanga2@gmail.com> Tested-by Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-11-30mips: octeon: tools: Add update_octeon_header toolStefan Roese2-222/+172
Add a tool to update or insert an Octeon specific header into the U-Boot image. This is needed e.g. for booting via SPI NOR, eMMC and NAND. While working on this, move enum cvmx_board_types_enum and cvmx_board_type_to_string() to cvmx-bootloader.h and remove the unreferenced (unsupported) board definition. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2020-11-30mips: octeon: bootoctlinux: Use gd->ram_size instead of ram_get_info()Stefan Roese1-18/+3
Using ram_get_info() is complicated and does not work after relocation. Now that gd->ram_size holds the full RAM size, let's use it instead and remove the ram_get_size logic completely. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2020-11-30mips: octeon: Report full DDR size in dram_init() to gd->ram_sizeStefan Roese1-1/+6
With this patch, gd->ram_size now holds to full RAM size detected by the DDR init code. It introduces the get_effective_memsize() function to report the maximum usable RAM size in U-Boot to the system instead. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2020-11-30mips: start.S: Add Octeon boot header compatibilityStefan Roese1-2/+8
Octeon has a specific boot header, when booted via SPI NOR, NAND or MMC. Here the only 2 instructions are allowed in the first few bytes of the image. And these instructions need to be one branch and a nop. This patch adds the necessary nop after the nop, to that the common MIPS image is compatible with this Octeon header. The tool to patch the Octeon boot header into the image will be send in a follow-up patch. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2020-10-07mips: octeon: Add bootoctlinux commandAaron Williams3-0/+716
Octeon needs a platform specific cmd to boot the Linux kernel, as specific parameters need to be passed and special handling for the multiple cores (SMP) is needed. Co-developed-by: Stefan Roese <sr@denx.de> Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> [use gd->ram_base instead of gd->bd->bi_memstart] Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2020-10-07mips: octeon: Add bootmem supportAaron Williams3-0/+1994
This is needed for Linux booting, as the memory infos need to be passed in this bootmem format to the Linux kernel. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2020-10-07mips: octeon: Add coremask supportAaron Williams3-0/+1119
This patch adds the coremask handling functions. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2020-10-07mips: octeon: Add header cvmx-bootinfo.hAaron Williams1-0/+350
Add header to handle bootinfo support, needed for Octeon Linux kernel booting. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2020-10-07mips: octeon: Add header cvmx-fuse.hAaron Williams1-0/+71
Add header to handle Octeon fuse access. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2020-10-07mips: octeon: Add header octeon-feature.hAaron Williams1-0/+442
This header includes the Octeon feature detection used in many Octeon drivers. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2020-10-07mips: octeon: Add header cvmx-regs.hAaron Williams1-0/+144
This header includes common register defines and accessor functions. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2020-10-07mips: octeon: lowlevel_init.S: Add NMI handling code for SMP Linux bootingStefan Roese1-0/+76
This patch adds the necessary lowlevel init code, to enable SMP Linux booting. This code will be used with the platform specific Octeon Linux boot command "bootoctlinux", which starts a configurable number of cores into Linux. Additionally some erratas and lowlevel register initializations are copied from the original Cavium / Marvell U-Boot source code, enabling booting into the Linux kernel. Signed-off-by: Stefan Roese <sr@denx.de>
2020-10-07mips: octeon: octeon-model.h: Enable inclusion from assembler filesStefan Roese1-0/+4
Add the #ifdef __ASSEMBLY__ checks to enable inclusion of this header from assembler files. Signed-off-by: Stefan Roese <sr@denx.de>
2020-10-07mips: octeon: Add USB DT nodesStefan Roese2-0/+84
Add the USB device tree nodes to the Octeon dts/dtsi files. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-10-07mips: octeon: cache.c: Flush all pending writes in flush_dcache_range()Stefan Roese1-6/+6
As noticed while working on the USB xHCI support, Octeon needs to flush all pending writes so that the values are present in the memory. Add this "syncw" instruction (twice) to flush_dcache_range(). Signed-off-by: Stefan Roese <sr@denx.de>
2020-10-07mips: octeon: Add mangle-port.hStefan Roese1-0/+56
Import platform specific mangle-port.h header, allowing a area specific swapping, which is needed on Octeon for USB & PCI areas. Imported from Linux v5.7. Signed-off-by: Stefan Roese <sr@denx.de>
2020-10-07mips: octeon: cpu.c: Add table for selective swappingStefan Roese1-0/+21
Import octeon_should_swizzle_table[] which is needed for the area specific swapping. It will be used by the platform specific mangle-port.h header. Imported from Linux v5.7. Signed-off-by: Stefan Roese <sr@denx.de>
2020-10-07mips: octeon: dram.c: Add RAM driver supportStefan Roese1-8/+64
This patch adds the initialization call for the Octeon RAM driver to the Octeon platforms code. So if enabled via Kconfig, the DDR driver will be called and the RAM will be configured and used. If the RAM driver is not enabled, the L2 cache is still used as RAM. Signed-off-by: Stefan Roese <sr@denx.de>
2020-10-07mips: octeon: Add octeon_ddr.h headerAaron Williams1-0/+982
This header will be used by the DDR driver (lmc). Its ported from the 2013 Cavium / Marvell U-Boot repository. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2020-10-07mips: octeon Add cvmx/cvmx-lmcx-defs.h headerAaron Williams1-0/+4574
This header will be used by the DDR driver (lmc). Its ported from the 2013 Cavium / Marvell U-Boot repository. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2020-10-07mips: octeon: Add octeon-model.h headerAaron Williams1-0/+313
This header is used by the upcoming DDR driver and potentially by other drivers ported from the 2013 Cavium / Marvell U-Boot repository. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2020-10-07mips: octeon: dts: mrvl, cn73xx.dtsi: Add memory controller DT nodeStefan Roese1-0/+17
This patch adds the memory controller (LMC) DT node to the Octeon 3 dtsi file. It also adds the L2C DT node, as this is referenced by the DDR driver. Signed-off-by: Stefan Roese <sr@denx.de>
2020-10-05Merge branch 'next'Tom Rini2-2/+2
Bring in the assorted changes that have been staged in the 'next' branch prior to release. Signed-off-by: Tom Rini <trini@konsulko.com>
2020-09-23mips: vocore2: fix various issuesMauro Condarelli1-1/+1
- fix SPL image generation - fix incorrect console output - increase malloc_f and malloc_r space to fix LZMA decompression errors - increase SPI flash clock Signed-off-by: Mauro Condarelli <mc5686@mclink.it> [squashed to one patch, fix commit subject and description] Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2020-09-23mips: dts: Fix PIC32MZDA GPIO register definitionsJohn Robertson1-2/+2
The GPIO bank name for banks J and K are not correct when using the 'gpio' command from the console. The driver derives the bank name from the device tree instance string by using the instance value and adding 'A': gpio0@xxaddrxx is Bank A, gpio1@yyaddryy is Bank B and so on. On the PIC32, there is no Bank I so instances 8 and 9 need to be incremented as a minimum change. An alternative (less opaque) implementation would be to use a bank-name property instead but this would require modifying the driver code too. Signed-off-by: John Robertson <john.robertson@simiatec.com>
2020-09-23mips: dts: Fix PIC32MZDA GPIO register definitionsJohn Robertson1-23/+22
GPIO state cannot be changed via the device tree (e.g. with gpio-hog) or using the 'gpio' command from the console. The root cause is a discrepancy between the driver and the device tree: the driver code expects an absolute I/O address in the <reg> property, while the device tree defines the address relative to a declaration in the parent pinctrl node. Changing the device tree to fix a driver issue would normally be wrong, however: - I have run the first version of U-Boot in which this driver appears (v2016.03) and the same problem exists, so this is not a regression; - There is no code that references a parent device tree node that might suggest the intent of the author was to parse the DT as it exists now; - The equivalent Linux PIC32 GPIO driver also uses absolute addresses for the GPIO <reg> property. This change brings the U-Boot DT more into line with Linux. Additionally, the data sheet (Microchip ref. 60001361H) shows that the register set to control a GPIO bank spans 0xE0 bytes, but the device tree specified size is only 0x48 bytes. Signed-off-by: John Robertson <john.robertson@simiatec.com>
2020-09-23mips: dts: Fix device tree warnings for PIC32MZDAJohn Robertson1-0/+11
Signed-off-by: John Robertson <john.robertson@simiatec.com>
2020-09-23mips: pic32mzdask: disable SDHCI SDCD signal workaroundJohn Robertson1-0/+1
The PIC32MZ DA Starter Kit does not need the card detect workaround because the SDCD signal line is connected properly. Disable the workaround in this case. Signed-off-by: John Robertson <john.robertson@simiatec.com>
2020-08-26global: Move from bi_memstart/memsize -> gd->ram_base/ram_sizeStefan Roese2-2/+2
With the planned removal of bi_memstart & bi_memsize, this patch now moves the references to the better suiting gd->ram_base/ram_size variables. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-04Merge tag 'mips-pull-2020-08-03' of ↵Tom Rini3-3/+90
https://gitlab.denx.de/u-boot/custodians/u-boot-mips - doc: fix qemu-mips build instructions - MIPS: add GPIO, CLK and SPI drivers for Octeon MIPS64
2020-08-04mscc: Drop dm.h header fileSimon Glass5-15/+0
This header file should not be included in other header files. Remove it from each one and use a forward declaration instead. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-08-03mips: octeon: Update Octeon KconfigStefan Roese1-2/+4
This patch selects DM_SPI & DM_I2C for MIPS Octeon. DM_GPIO, DM_SERIAL and DM_ETH are already selected. Additionally the selections are now alphabetically sorted. Signed-off-by: Stefan Roese <sr@denx.de>
2020-08-03mips: octeon: mrvl, octeon-ebb7304.dts: Add SPI flash DT nodeStefan Roese1-0/+9
Add the SPI flash DT node for the EBB7304. Signed-off-by: Stefan Roese <sr@denx.de>
2020-08-03mips: octeon: mrvl,cn73xx.dtsi: Add SPI DT nodeStefan Roese1-0/+10
Add the Octeon SPI DT node to the dtsi file. Signed-off-by: Stefan Roese <sr@denx.de>
2020-08-03mips: octeon: dts: Add Octeon clock driver DT nodesStefan Roese2-1/+11
This patch adds the DT nodes for the Octeon clock support via the common clk_ API. Signed-off-by: Stefan Roese <sr@denx.de>
2020-08-03mips: octeon: dts: Add I2C DT nodesStefan Roese2-0/+30
Add I2C DT nodes to the Octeon dts / dtsi files. Signed-off-by: Stefan Roese <sr@denx.de>
2020-08-03mips: octeon: mrvl,cn73xx.dtsi: Add GPIO DT nodesStefan Roese1-0/+26
Add the Octeon GPIO DT node to the dtsi file. Signed-off-by: Stefan Roese <sr@denx.de>
2020-07-18mips: octeon: Add minimal Octeon 3 EBB7304 EVK supportStefan Roese3-0/+111
This patch adds very basic minimal support for the Marvell Octeon 3 CN73xx based EBB7304 EVK. Please note that the basic Octeon port does not support DDR3/4 initialization yet. To still use U-Boot on with this port, the L2 cache (4MiB) is used as RAM. This way, U-Boot can boot to the prompt on this board. Supported devices: - UART - reset - CFI parallel NOR flash Signed-off-by: Stefan Roese <sr@denx.de>
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