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2020-05-19common: Drop linux/delay.h from common headerSimon Glass1-0/+1
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-19common: Drop log.h from common headerSimon Glass1-0/+1
Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2019-12-03common: Move some time functions out of common.hSimon Glass1-0/+1
These functions belong in time.h so move them over and add comments. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-08-11env: Move env_get_f() to env.hSimon Glass1-0/+1
Move this function over to the new header file. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-05-07SPDX: Convert all of our single license tags to Linux Kernel styleTom Rini1-2/+1
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2017-08-16env: Rename getenv/_f() to env_get()Simon Glass1-1/+1
We are now using an env_ prefix for environment functions. Rename these two functions for consistency. Also add function comments in common.h. Quite a few places use getenv() in a condition context, provoking a warning from checkpatch. These are fixed up in this patch also. Suggested-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Simon Glass <sjg@chromium.org>
2016-11-30Merge git://git.denx.de/u-boot-mpc85xxTom Rini1-3/+3
2016-11-24powerpc: P5040: Remove macro CONFIG_P5040York Sun1-2/+2
Replace CONFIG_P5040 with ARCH_P5040 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-24powerpc: P4080: Remove macro CONFIG_PPC_P4080York Sun1-1/+1
Replace CONFIG_PPC_P4080 with ARCH_P4080 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-21fsl: serdes: fix a deadloop issue for P4080Hou Zhiqiang1-3/+3
This deadloop is introduced by commit: 71fe222 fsl: serdes: ensure accessing the initialized maps of serdes protocol deadloop detail: cpu_init_r => fsl_serdes_init => p4080_erratum_serdes_a005 => is_serdes_configured => fsl_serdes_init Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-09-27Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini1-0/+8
trini: Drop local memset() from examples/standalone/mem_to_mem_idma2intr.c Signed-off-by: Tom Rini <trini@konsulko.com>
2016-09-24treewide: replace #include <asm/errno.h> with <linux/errno.h>Masahiro Yamada1-1/+1
Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have the same content. (both just wrap <asm-generic/errno.h>) Replace all include directives for <asm/errno.h> with <linux/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> [trini: Fixup include/clk.] Signed-off-by: Tom Rini <trini@konsulko.com>
2016-09-15fsl: serdes: ensure accessing the initialized maps of serdes protocolHou Zhiqiang1-0/+8
Up to now, the function is_serdes_configed() doesn't check if the map of serdes protocol is initialized before accessing it. The function is_serdes_configed() will get wrong result when it was called before the serdes protocol maps initialized. As the first element of the map isn't used for any device, so use it as the flag to indicate if the map has been initialized. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2013-10-24fsl/mpc85xx: define common serdes_clock_to_string functionValentin Longchamp1-0/+17
This allows to share some common code for the boards that use a corenet base SoC. Two different versions of the function are available in fsl_corenet_serdes.c and fsl_corenet2_serdes.c files. Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> [York Sun: fix t1040qds.c] Acked-by: York Sun <yorksun@freescale.com>
2013-07-24Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk1-17/+1
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
2013-05-03powerpc/85xx: add SerDes bank 4 lanesTimur Tabi1-0/+4
Only some chips have four SerDes banks, so don't define lanes for a bank that doesn't exist. Signed-off-by: Timur Tabi <timur@tabi.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-04-02Consolidate bool typeYork Sun1-1/+1
'bool' is defined in random places. This patch consolidates them into a single header file include/linux/types.h, using stdbool.h introduced in C99. All other #define, typedef and enum are removed. They are all consistent with true = 1, false = 0. Replace FALSE, False with false. Replace TRUE, True with true. Skip *.py, *.php, lib/* files. Signed-off-by: York Sun <yorksun@freescale.com>
2012-11-28powerpc/85xx: update the work-around for P4080 erratum SERDES-9Timur Tabi1-7/+13
The documented work-around for P4080 erratum SERDES-9 has been updated. It is now compatible with the work-around for erratum A-4580. This requires adding a few bitfield macros for the BnTTLCRy0 register. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-11-04powerpc/mpc85xx: sparse fixesKim Phillips1-1/+1
fsl_corenet_serdes.c:485:6: warning: symbol '__soc_serdes_init' was not declared. Should it be static? cpu_init.c:185:6: warning: symbol 'invalidate_cpc' was not declared. Should it be static? bcsr.c:28:27: warning: non-ANSI function declaration of function 'enable_8568mds_duart' bcsr.c:39:33: warning: non-ANSI function declaration of function 'enable_8568mds_flash_write' bcsr.c:46:34: warning: non-ANSI function declaration of function 'disable_8568mds_flash_write' bcsr.c:53:29: warning: non-ANSI function declaration of function 'enable_8568mds_qe_mdio' bcsr.c:28:33: warning: non-ANSI function declaration of function 'enable_8569mds_flash_write' bcsr.c:33:34: warning: non-ANSI function declaration of function 'disable_8569mds_flash_write' bcsr.c:38:28: warning: non-ANSI function declaration of function 'enable_8569mds_qe_uec' bcsr.c:63:47: warning: non-ANSI function declaration of function 'disable_8569mds_brd_eeprom_write_protect' ngpixis.c:245:1: error: directive in argument list ngpixis.c:247:1: error: directive in argument list Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2012-10-22powerpc/85xx: Add P5040 processor supportTimur Tabi1-0/+70
Add support for the Freescale P5040 SOC, which is similar to the P5020. Features of the P5040 are: Four P5040 single-threaded e5500 cores built Up to 2.4 GHz with 64-bit ISA support Three levels of instruction: user, supervisor, hypervisor CoreNet platform cache (CPC) 2.0 MB configures as dual 1 MB blocks hierarchical interconnect fabric Two 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving support Up to 1600MT/s Memory pre-fetch engine DPAA incorporating acceleration for the following functions Packet parsing, classification, and distribution (FMAN) Queue management for scheduling, packet sequencing and congestion management (QMAN) Hardware buffer management for buffer allocation and de-allocation (BMAN) Cryptography acceleration (SEC 5.2) at up to 40 Gbps SerDes 20 lanes at up to 5 Gbps Supports SGMII, XAUI, PCIe rev1.1/2.0, SATA Ethernet interfaces Two 10 Gbps Ethernet MACs Ten 1 Gbps Ethernet MACs High-speed peripheral interfaces Two PCI Express 2.0/3.0 controllers Additional peripheral interfaces Two serial ATA (SATA 2.0) controllers Two high-speed USB 2.0 controllers with integrated PHY Enhanced secure digital host controller (SD/MMC/eMMC) Enhanced serial peripheral interface (eSPI) Two I2C controllers Four UARTs Integrated flash controller supporting NAND and NOR flash DMA Dual four channel Support for hardware virtualization and partitioning enforcement Extra privileged level for hypervisor support QorIQ Trust Architecture 1.1 Secure boot, secure debug, tamper detection, volatile key storage Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23powerpc/mpc8xxx: Move HWCONFIG_BUFFER_SIZE into config.hYork Sun1-2/+0
Before proper environment is setup, we extract hwconfig and put it into a buffer with size HWCONFIG_BUFFER_SIZE. We need to enlarge the buffer to accommodate longer string. Since this macro is used in multiple files, we move it into arch/powerpc/include/asm/config.h. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23powerpc/85xx: add support for FM2 DTSEC5Timur Tabi1-0/+6
Unlike previous SOCs, the Freescale P5040 has a fifth DTSEC on the second Fman, so add the Fman and SerDes macros for that DTSEC. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2011-11-11arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c: Fix GCC 4.6 build warningKumar Gala1-1/+6
Fix: fsl_corenet_serdes.c: In function 'fsl_serdes_init': fsl_corenet_serdes.c:511:8: warning: variable 'buf' set but not used [-Wunused-but-set-variable] fsl_corenet_serdes.c:498:18: warning: variable 'lane_prtcl' set but not used [-Wunused-but-set-variable] Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-21powerpc/85xx: wait for alignment before resetting SERDES RX lanes (SERDES9)Timur Tabi1-10/+0
The work-around for P4080 erratum SERDES9 says that the SERDES receiver lanes should be reset after the XAUI starts tranmitting alignment signals. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-03powerpc/p3060: Add SoC related support for P3060 platformShengzhou Liu1-0/+9
Add P3060 SoC specific information:cores setup, LIODN setup, etc The P3060 SoC combines six e500mc Power Architecture processor cores with high-performance datapath acceleration architecture(DPAA), CoreNet fabric infrastructure, as well as network and peripheral interfaces. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-11powerpc/85xx: remove SERDES4 soft-reset work-aroundTimur Tabi1-22/+49
Some P4080 rev1 errata work-arounds, notably erratum SERDES4, required a bank soft-reset after the bank was configured and enabled, even though enabling a bank causes it to reset. Because the reset was required for multiple errata, it was not properly enclosed in an #ifdef, and so was not removed with all the other rev1 errata work-arounds. Erratum SERDES-8 says that the clocks for bank 3 needs to be enabled if bank 2 is enabled, but this was not being done for SERDES protocols 0xF and 0x10. The bank reset also happened to enable bank 3 (apparently an undocumented feature). Simply removing the reset breaks these two protocols. It turns out that every time we call enable_bank(), we do want at least one lane of the bank enabled, either because the bank is supposed to be enabled, or because we need the clock from that bank enabled. For erratum SERDES-A001, we don't want to modify srds_lpd_b[] when we call enable_bank(), because that array is used elsewhere to determine if the bank is available. Note that the side effect of these changes is that the work-arounds for these two errata are now linked. Specifically, if SERDES-A001 is enabled, then we need SERDES-8 enabled as well. Because this was the only SERDES bank soft-reset, there is no need to implement a work-around for erratum SERDES-A003. Also fix an off-by-one error in a printf(). Signed-off-by: Timur Tabi <timur@freescale.com> Acked-by: Ed Swarthout <swarthou@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-29powerpc/85xx: Implement work-around for P4080 erratum SERDES-A001Timur Tabi1-16/+64
Bank powerdown through RCW[SRDS_LPD_Bn] for XAUI on FM2 and SGMII on FM1 are swapped. Erratum SERDES-A001 says that if bank two is kept disabled and after bank three is enabled, then the PLL for bank three won't lock properly. The work-around is to enable and then disable bank two after bank three is enabled. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-29powerpc/85xx: Extend SERDES9 erratum work-around to SGMII, SRIO, and AURORATimur Tabi1-17/+34
Part of the SERDES9 erratum work-around is to set some bits in the SerDes TTLCR0 register for lanes configured as XAUI, SGMII, SRIO, or AURORA. The current code does this only for XAUI, so extend it to the other protocols. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-29powerpc/85xx: Display SERDES 8 erratum warning if banks are not disabledTimur Tabi1-0/+11
The work-around for P4080 erratum SERDES-8 requires all lanes of banks two and three to be disabled (powered down) in the RCW. Display a warning message if this is not the case. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-29powerpc/85xx: Implement work-around for P4080 erratum SERDES-A005Timur Tabi1-0/+48
SerDes PLL bandwidth default setting is incorrect when no lanes are configured as PCI Express. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-28p4080/serdes: Implement the XAUI workaround for SERDES9 erratumEmil Medve1-0/+107
Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-28powerpc/85xx: fsl_corenet_serdes code reworkEmil Medve1-2/+38
Rework and add some new APIs to the fsl_corenet_serdes code for use by erratum and drivers. * Rename serdes_get_bank() to serdes_get_bank_by_lane() * Add serdes_get_first_lane returns which SERDES lane is used by device Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-10p4080ds: remove rev1-specific code for the SERDES8 erratumTimur Tabi1-59/+47
Remove the SERDES8 erratum work-around code that only applied to P4080 rev1, which is not supported by this version of U-Boot. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-20powerpc/p4080: Fix warning in serdes code from early use of hwconfigYork Sun1-3/+14
Hwconfig is called before relocating. Use the new hwconfig APIs. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-26powerpc/p4080: Add workaround for errata SERDES8Kumar Gala1-0/+283
Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-07-26powerpc/p4080: Add support for initializing SERDESKumar Gala1-0/+212
Add support for initializing the SERDES blocks on CoreNet style QoriQ devices and the p4080 specific SERDES tables to know which actual componetns are enabled. Additionally, split out the Frame Manger (FMAN) into its specific ethernet ports instead of gross level of the full FMAN. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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