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starfive-tech/u-boot.git
Fedora_JH7100_2021.04
Fedora_JH7100_2021.07
Fedora_JH7100_upstream
Fedora_JH7100_upstream_devel
JH7100_Multimedia_V0.1.0
JH7100_VisionFive_OH_dev
JH7100_VisionFive_devel
JH7100_starlight_multimedia
JH7100_upstream
JH7100_upstream_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_devel-v3.9.3
dubhe_fpga_dev_v2023.10
master
rtthread_AMP
visionfive_devel
StarFive Tech U-Boot for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
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/
arch
/
riscv
/
cpu
/
cpu.c
Age
Commit message (
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)
Author
Files
Lines
2023-08-22
riscv: cpu: make riscv_cpu_probe to EVT_DM_POST_INIT_R callback
Chanho Park
1
-8
/
+3
2023-05-11
dm: Emit the arch_cpu_init_dm() even only before relocation
Simon Glass
1
-1
/
+1
2023-02-01
riscv: cpu: check U-Mode before counteren write
Nikita Shubin
1
-8
/
+8
2022-11-15
riscv: Fix detecting FPU support in standard extension
Yu Chien Peter Lin
1
-3
/
+11
2022-09-26
riscv: Introduce AVAILABLE_HARTS
Rick Chen
1
-0
/
+2
2022-09-26
spl: introduce SPL_XIP to config
Nikita Shubin
1
-1
/
+1
2022-03-10
event: Convert arch_cpu_init_dm() to use events
Simon Glass
1
-1
/
+4
2021-10-18
riscv: Remove OF_PRIOR_STAGE from RISC-V boards
Ilias Apalodimas
1
-3
/
+0
2021-10-07
sysreset: provide SBI based sysreset driver
Heinrich Schuchardt
1
-1
/
+12
2021-05-24
treewide: Convert macro and uses of __section(foo) to __section("foo")
Marek BehĂșn
1
-2
/
+2
2021-05-05
riscv: cpu: Add callback to init each core
Green Wan
1
-0
/
+11
2020-09-30
riscv: Clear pending IPIs on initialization
Sean Anderson
1
-0
/
+20
2020-07-24
riscv: Make SiFive HiFive Unleashed board boot again
Bin Meng
1
-1
/
+1
2020-07-01
riscv: Add option to support RISC-V privileged spec 1.9
Sean Anderson
1
-0
/
+9
2020-07-01
riscv: Clean up IPI initialization code
Sean Anderson
1
-0
/
+6
2020-05-19
common: Drop linux/bitops.h from common header
Simon Glass
1
-0
/
+1
2020-05-19
common: Drop init.h from common header
Simon Glass
1
-0
/
+1
2019-08-26
riscv: add run mode configuration for SPL
Lukas Auer
1
-3
/
+3
2019-08-15
riscv: Access CSRs using CSR numbers
Bin Meng
1
-5
/
+4
2019-05-09
riscv: prior_stage_fdt_address should only be used when OF_PRIOR_STAGE is ena...
Rick Chen
1
-0
/
+2
2019-05-09
riscv: Introduce CONFIG_XIP to support booting from flash
Rick Chen
1
-0
/
+2
2019-04-08
riscv: add support for multi-hart systems
Lukas Auer
1
-1
/
+8
2018-12-18
riscv: Do some basic architecture level cpu initialization
Bin Meng
1
-1
/
+26
2018-12-18
riscv: Update supports_extension() to use desc from cpu driver
Bin Meng
1
-0
/
+26
2018-12-18
riscv: Remove non-DM version of print_cpuinfo()
Bin Meng
1
-37
/
+0
2018-12-18
riscv: Probe cpus during boot
Bin Meng
1
-0
/
+26
2018-11-26
riscv: save hart ID and device tree passed by prior boot stage
Lukas Auer
1
-0
/
+6
2018-10-03
riscv: Add a helper routine to print CPU information
Bin Meng
1
-0
/
+49