Age | Commit message (Expand) | Author | Files | Lines |
---|---|---|---|---|
2021-05-19 | riscv: qemu: Switch to use binman to generate u-boot.itb | Bin Meng | 1 | -0/+1 |
2021-05-17 | riscv: Split SiFive CLINT support between SPL and U-Boot proper | Bin Meng | 1 | -1/+2 |
2021-03-27 | cpu: Rename SPL_CPU_SUPPORT to SPL_CPU | Simon Glass | 1 | -1/+1 |
2020-09-30 | riscv: Rework riscv timer driver to only support S-mode | Sean Anderson | 1 | -1/+1 |
2019-08-26 | riscv: add SPL support | Lukas Auer | 1 | -0/+3 |
2019-08-26 | riscv: add run mode configuration for SPL | Lukas Auer | 1 | -1/+1 |
2019-02-27 | riscv: Rename cpu/qemu to cpu/generic | Anup Patel | 1 | -0/+12 |