starfive-tech/u-boot.git - StarFive Tech U-Boot for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2020-09-30	riscv: Add some comments to start.S	Sean Anderson	1	-2/+17
2020-09-30	riscv: Ensure gp is NULL or points to valid data	Sean Anderson	1	-3/+25
2020-09-30	riscv: Consolidate fences into AMOs for available_harts_lock	Sean Anderson	1	-6/+3
2020-09-30	riscv: Clear pending IPIs on initialization	Sean Anderson	1	-0/+20
2020-09-30	Revert "riscv: Clear pending interrupts before enabling IPIs"	Sean Anderson	1	-2/+0
2020-09-30	riscv: Rework riscv timer driver to only support S-mode	Sean Anderson	3	-3/+3
2020-08-25	riscv: fu540: Use correct API to get L2 cache controller base address	Bin Meng	1	-1/+2
2020-08-14	riscv: sifive: fu540: redundant initialization	Heinrich Schuchardt	1	-1/+1
2020-08-14	riscv: sifive/fu540: kconfig: Move FU540 driver related options to the SoC level	Bin Meng	1	-0/+22
2020-08-14	riscv: sifive/fu540: spl: Rename soc_spl_init()	Bin Meng	1	-1/+1
2020-07-24	riscv: Fix linking error when building u-boot-spl with no SMP support	Leo Yu-Chi Liang	1	-0/+2
2020-07-24	env: Enable SPI flash env for SiFive FU540	Jagan Teki	1	-0/+13
2020-07-24	riscv: Make SiFive HiFive Unleashed board boot again	Bin Meng	1	-1/+1
2020-07-06	Merge branch 'next'	Tom Rini	2	-0/+17
2020-07-03	riscv: sifive: fu540: enable all cache ways from U-Boot proper	Pragnesh Patel	2	-0/+54
2020-07-01	riscv: Add option to support RISC-V privileged spec 1.9	Sean Anderson	1	-0/+9
2020-07-01	riscv: Clean up IPI initialization code	Sean Anderson	1	-0/+6
2020-07-01	riscv: Clear pending interrupts before enabling IPIs	Sean Anderson	1	-0/+2
2020-06-04	riscv: sifive: fu540: add SPL configuration	Pragnesh Patel	2	-0/+27
2020-06-04	riscv: cpu: fu540: Add support for cpu fu540	Pragnesh Patel	4	-0/+82
2020-06-04	riscv: Add _image_binary_end for SPL	Pragnesh Patel	1	-0/+1
2020-05-19	common: Drop linux/bitops.h from common header	Simon Glass	1	-0/+1
2020-05-19	common: Drop init.h from common header	Simon Glass	1	-0/+1
2020-05-19	common: Drop net.h from common header	Simon Glass	2	-0/+2
2020-04-23	riscv: Provide a mechanism to fix DT for reserved memory	Atish Patra	1	-0/+1
2020-04-23	riscv: Introduce SPL_SMP Kconfig option for U-Boot SPL	Bin Meng	1	-7/+7
2020-04-23	riscv: Merge unnecessary SMP ifdefs in start.S	Bin Meng	1	-4/+0
2020-04-23	riscv: qemu: Remove the simple-bus driver for the SoC node	Bin Meng	1	-14/+0
2020-04-23	riscv: ax25: cache: Remove SPL_RISCV_MMODE config check	Pragnesh Patel	1	-8/+8
2020-02-10	riscv: Remove unnecessary instruction	Sean Anderson	1	-3/+2
2020-02-10	riscv: Add option to print registers on exception	Sean Anderson	1	-1/+2
2020-02-10	riscv: Fix breakage caused by linker relaxation	Sean Anderson	1	-1/+0
2020-01-17	common: Move relocate_code() to init.h	Simon Glass	1	-1/+1
2019-12-10	riscv: add option to wait for ack from secondary harts in smp functions	Lukas Auer	1	-0/+2
2019-12-10	riscv: Fix clear bss loop in the start-up code	Rick Chen	3	-4/+4
2019-12-10	riscv: ax25: cache: Add SPL_RISCV_MMODE for SPL	Rick Chen	1	-14/+46
2019-12-10	riscv: ax25: add SPL support	Rick Chen	1	-1/+3
2019-12-03	common: Move board_get_usable_ram_top() out of common.h	Simon Glass	1	-0/+1
2019-12-03	common: Move enable/disable_interrupts out of common.h	Simon Glass	1	-0/+1
2019-12-03	common: Move ARM cache operations out of common.h	Simon Glass	1	-0/+1
2019-12-03	common: Move some cache and MMU functions out of common.h	Simon Glass	2	-0/+2
2019-09-03	riscv: cache: use CCTL to flush d-cache	Rick Chen	1	-9/+13
2019-09-03	riscv: cache: Flush L2 cache before jump to linux	Rick Chen	1	-0/+17
2019-09-03	riscv: ax25: add imply v5l2 cache controller	Rick Chen	1	-0/+1
2019-09-03	riscv: update fix_rela_dyn	Marcus Comstedt	1	-5/+5
2019-08-26	riscv: support SPL stack and global data relocation	Lukas Auer	1	-1/+34
2019-08-26	riscv: add SPL support	Lukas Auer	3	-1/+107
2019-08-26	riscv: add run mode configuration for SPL	Lukas Auer	4	-10/+10
2019-08-15	riscv: Access CSRs using CSR numbers	Bin Meng	2	-7/+5
2019-05-18	CONFIG_SPL_SYS_[DI]CACHE_OFF: add	Trevor Woerner	1	-4/+4