starfive-tech/u-boot.git - StarFive Tech U-Boot for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2023-07-20	board: starfive: evb: use dram_init in spl	Samin Guo	2	-1/+7
2023-07-18	dram: jh7110: remove resize-ddr function	Samin Guo	1	-40/+10
2023-07-10	dram: starfive: jh7110: Add 1G support	Samin Guo	1	-0/+1
2023-07-10	dram: jh7110: Add CONFIG_ID_EEPROM to determine if EEPROM is available	Samin Guo	1	-18/+26
2023-07-10	dram: jh7110: Macro definitions STARFIVE_JH7110_EEPROM_DDRINFO_OFFSET	Samin Guo	1	-1/+2
2023-06-25	dram: jh7110: Add resize DDR info from EEPROM.	Samin Guo	1	-2/+47
2023-04-23	board: starfive: copyright: Standardize the copyright format	Yanhong Wang	2	-2/+2
2023-02-21	riscv:uboot:cache driver	keith.zhao	1	-1/+1
2023-02-17	riscv:cache:jh7110: add cache driver	keith.zhao	3	-0/+66
2023-02-02	sysreset: provide SBI based sysreset driver	Heinrich Schuchardt	1	-1/+12
2022-12-14	board:starfive:jh7110: default cpufreq is 1000Mhz.	Samin Guo	1	-1/+1
2022-10-18	arch: riscv: jh7110: add pll clk configuration for jh7110	Yan Hong Wang	2	-0/+380
2022-10-18	riscv:starfive-jh7110: clear L2 LIM memory	yanhong.wang	1	-0/+14
2022-10-18	riscv:soc:jh7110: Add support jh7110 soc.	yanhong.wang	5	-0/+165
2021-09-07	board: sifive: use ccache driver instead of helper function	Zong Li	6	-112/+4
2021-08-17	riscv: cpu: fu740: Fix typo of date	Zong Li	1	-1/+1
2021-07-28	i2c: Rename SPL/TPL_I2C_SUPPORT to I2C	Simon Glass	1	-1/+1
2021-07-06	riscv: sifive: fu740: Support i2c in spl	Zong Li	1	-0/+1
2021-07-06	riscv: sifive: fu740: kconfig: Enable support for Opencores I2C controller	Zong Li	1	-0/+2
2021-05-31	riscv: cpu: fu740: clear feature disable CSR	Green Wan	1	-0/+15
2021-05-31	drivers: clk: add fu740 support	Green Wan	1	-1/+1
2021-05-31	riscv: cpu: fu740: Add support for cpu fu740	Green Wan	6	-0/+187
2021-05-24	treewide: Convert macro and uses of __section(foo) to __section("foo")	Marek Behún	1	-2/+2
2021-05-19	riscv: qemu: Switch to use binman to generate u-boot.itb	Bin Meng	1	-0/+1
2021-05-17	riscv: Split SiFive CLINT support between SPL and U-Boot proper	Bin Meng	2	-2/+3
2021-05-14	Revert "riscv: cpu: fu740: clear feature disable CSR"	Bin Meng	1	-15/+0
2021-05-05	riscv: cpu: fu740: clear feature disable CSR	Green Wan	1	-0/+15
2021-05-05	riscv: cpu: Add callback to init each core	Green Wan	2	-0/+15
2021-03-27	cpu: Rename SPL_CPU_SUPPORT to SPL_CPU	Simon Glass	3	-3/+3
2021-02-15	Merge branch '2021-02-02-drop-asm_global_data-when-unused'	Tom Rini	3	-0/+3
2021-02-03	riscv: Adjust board_get_usable_ram_top() for 32-bit	Bin Meng	2	-8/+6
2021-02-02	common: Drop asm/global_data.h from common header	Simon Glass	3	-0/+3
2020-12-14	riscv: fix the wrong swap value register	Brad Kim	1	-1/+1
2020-11-28	riscv: sifive/fu540: kconfig: Enable support for Opencores I2C controller	Pragnesh Patel	1	-0/+2
2020-10-26	timer: Add _TIMER suffix to Andes PLMT Kconfig	Sean Anderson	1	-1/+1
2020-09-30	riscv: Add some comments to start.S	Sean Anderson	1	-2/+17
2020-09-30	riscv: Ensure gp is NULL or points to valid data	Sean Anderson	1	-3/+25
2020-09-30	riscv: Consolidate fences into AMOs for available_harts_lock	Sean Anderson	1	-6/+3
2020-09-30	riscv: Clear pending IPIs on initialization	Sean Anderson	1	-0/+20
2020-09-30	Revert "riscv: Clear pending interrupts before enabling IPIs"	Sean Anderson	1	-2/+0
2020-09-30	riscv: Rework riscv timer driver to only support S-mode	Sean Anderson	3	-3/+3
2020-08-25	riscv: fu540: Use correct API to get L2 cache controller base address	Bin Meng	1	-1/+2
2020-08-14	riscv: sifive: fu540: redundant initialization	Heinrich Schuchardt	1	-1/+1
2020-08-14	riscv: sifive/fu540: kconfig: Move FU540 driver related options to the SoC level	Bin Meng	1	-0/+22
2020-08-14	riscv: sifive/fu540: spl: Rename soc_spl_init()	Bin Meng	1	-1/+1
2020-07-24	riscv: Fix linking error when building u-boot-spl with no SMP support	Leo Yu-Chi Liang	1	-0/+2
2020-07-24	env: Enable SPI flash env for SiFive FU540	Jagan Teki	1	-0/+13
2020-07-24	riscv: Make SiFive HiFive Unleashed board boot again	Bin Meng	1	-1/+1
2020-07-06	Merge branch 'next'	Tom Rini	2	-0/+17
2020-07-03	riscv: sifive: fu540: enable all cache ways from U-Boot proper	Pragnesh Patel	2	-0/+54