index
:
starfive-tech/u-boot.git
Fedora_JH7100_2021.04
Fedora_JH7100_2021.07
Fedora_JH7100_upstream
Fedora_JH7100_upstream_devel
JH7100_Multimedia_V0.1.0
JH7100_VisionFive_OH_dev
JH7100_VisionFive_devel
JH7100_starlight_multimedia
JH7100_upstream
JH7100_upstream_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_devel-v3.9.3
dubhe_fpga_dev_v2023.10
master
rtthread_AMP
visionfive_devel
StarFive Tech U-Boot for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
arch
/
riscv
/
cpu
Age
Commit message (
Expand
)
Author
Files
Lines
2020-04-23
riscv: Merge unnecessary SMP ifdefs in start.S
Bin Meng
1
-4
/
+0
2020-04-23
riscv: qemu: Remove the simple-bus driver for the SoC node
Bin Meng
1
-14
/
+0
2020-04-23
riscv: ax25: cache: Remove SPL_RISCV_MMODE config check
Pragnesh Patel
1
-8
/
+8
2020-02-10
riscv: Remove unnecessary instruction
Sean Anderson
1
-3
/
+2
2020-02-10
riscv: Add option to print registers on exception
Sean Anderson
1
-1
/
+2
2020-02-10
riscv: Fix breakage caused by linker relaxation
Sean Anderson
1
-1
/
+0
2020-01-17
common: Move relocate_code() to init.h
Simon Glass
1
-1
/
+1
2019-12-10
riscv: add option to wait for ack from secondary harts in smp functions
Lukas Auer
1
-0
/
+2
2019-12-10
riscv: Fix clear bss loop in the start-up code
Rick Chen
3
-4
/
+4
2019-12-10
riscv: ax25: cache: Add SPL_RISCV_MMODE for SPL
Rick Chen
1
-14
/
+46
2019-12-10
riscv: ax25: add SPL support
Rick Chen
1
-1
/
+3
2019-12-03
common: Move board_get_usable_ram_top() out of common.h
Simon Glass
1
-0
/
+1
2019-12-03
common: Move enable/disable_interrupts out of common.h
Simon Glass
1
-0
/
+1
2019-12-03
common: Move ARM cache operations out of common.h
Simon Glass
1
-0
/
+1
2019-12-03
common: Move some cache and MMU functions out of common.h
Simon Glass
2
-0
/
+2
2019-09-03
riscv: cache: use CCTL to flush d-cache
Rick Chen
1
-9
/
+13
2019-09-03
riscv: cache: Flush L2 cache before jump to linux
Rick Chen
1
-0
/
+17
2019-09-03
riscv: ax25: add imply v5l2 cache controller
Rick Chen
1
-0
/
+1
2019-09-03
riscv: update fix_rela_dyn
Marcus Comstedt
1
-5
/
+5
2019-08-26
riscv: support SPL stack and global data relocation
Lukas Auer
1
-1
/
+34
2019-08-26
riscv: add SPL support
Lukas Auer
3
-1
/
+107
2019-08-26
riscv: add run mode configuration for SPL
Lukas Auer
4
-10
/
+10
2019-08-15
riscv: Access CSRs using CSR numbers
Bin Meng
2
-7
/
+5
2019-05-18
CONFIG_SPL_SYS_[DI]CACHE_OFF: add
Trevor Woerner
1
-4
/
+4
2019-05-09
riscv: prior_stage_fdt_address should only be used when OF_PRIOR_STAGE is ena...
Rick Chen
2
-0
/
+4
2019-05-09
riscv: Introduce CONFIG_XIP to support booting from flash
Rick Chen
2
-0
/
+8
2019-04-08
riscv: ax25: Andes specific cache shall only support in M-mode
Rick Chen
1
-0
/
+1
2019-04-08
riscv: ax25: Add platform-specific Kconfig options
Rick Chen
1
-0
/
+6
2019-04-08
riscv: hang if relocation of secondary harts fails
Lukas Auer
1
-1
/
+12
2019-04-08
riscv: do not rely on hart ID passed by previous boot stage
Lukas Auer
1
-0
/
+4
2019-04-08
riscv: add support for multi-hart systems
Lukas Auer
2
-2
/
+141
2019-04-08
riscv: save hart ID in register tp instead of s0
Lukas Auer
1
-2
/
+2
2019-04-08
riscv: delay initialization of caches and debug UART
Lukas Auer
1
-8
/
+8
2019-02-27
riscv: generic: Ensure that U-Boot runs within 4GB for 64bit systems
Anup Patel
1
-0
/
+20
2019-02-27
riscv: Rename cpu/qemu to cpu/generic
Anup Patel
4
-1
/
+1
2019-01-15
riscv: move the AX25-specific implementation of flush_dcache_all
Lukas Auer
1
-0
/
+22
2018-12-18
riscv: Save boot hart id to the global data
Bin Meng
1
-0
/
+4
2018-12-18
riscv: Return to previous privilege level after trap handling
Bin Meng
1
-8
/
+0
2018-12-18
riscv: Fix context restore before returning from trap handler
Bin Meng
1
-1
/
+1
2018-12-18
riscv: Move trap handler codes to mtrap.S
Bin Meng
3
-90
/
+112
2018-12-18
riscv: Do some basic architecture level cpu initialization
Bin Meng
1
-1
/
+26
2018-12-18
riscv: Update supports_extension() to use desc from cpu driver
Bin Meng
1
-0
/
+26
2018-12-18
riscv: Remove non-DM version of print_cpuinfo()
Bin Meng
1
-37
/
+0
2018-12-18
riscv: Probe cpus during boot
Bin Meng
2
-0
/
+27
2018-12-18
riscv: qemu: Add platform-specific Kconfig options
Bin Meng
1
-0
/
+11
2018-12-18
riscv: ax25: Hide the ax25-specific Kconfig option
Bin Meng
2
-11
/
+18
2018-12-18
riscv: qemu: Create a simple-bus driver for the soc node
Bin Meng
1
-0
/
+14
2018-12-05
riscv: ax25-ae350: Pass dtb address to u-boot with a1 register
Rick Chen
1
-2
/
+0
2018-12-05
riscv: Add kconfig option to run U-Boot in S-mode
Anup Patel
1
-8
/
+15
2018-11-26
riscv: cache: Implement i/dcache [status, enable, disable]
Rick Chen
6
-1
/
+114
[prev]
[next]