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2022-01-13riscv: dts: starfive: add watchdog nodeHal Feng1-0/+14
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2022-01-11riscv: dts: starfive: Modify devicee tree for VisionFive to support WM8960 ↵Som Qin1-2/+2
daughter board Modify the gpio node to keep i2s pins state. Signed-off-by: Som Qin <som.qin@starfivetech.com>
2022-01-07dts: fixed libcamera report locaton warning about imx219Andy Hu1-0/+2
Signed-off-by: 123curry <curry.zhang@starfivetech.com>
2022-01-05starfive: apply VisionFive board changesSom.Qin1-0/+15
The VisionFive dts is base on Starlight dts, and the difference of rst gpio, eeprom and gmac should be applied. Signed-off-by: Som.Qin <som.qin@starfivetech.com>
2021-12-30starfive: add JH7100 VisionFive V1 Support.Jianlong.Huang2-0/+18
Signed-off-by: Jianlong.Huang <jianlong.huang@starfivetech.com>
2021-09-29starfive(multimedia): Add pwmdac pinctl and keep 0,2,3,45 gpio for i2s to dtssw.multimedia2-6/+25
2021-09-29starfive(multimedia): apply starfive v4l2 pinctl to dtssw.multimedia3-5/+119
Signed-off-by: sw.multimedia <sw.multimedia@starfivetech.com>
2021-09-29starfive: apply the pinctl to dtssw.multimedia2-12/+323
2021-09-29starfive: Add v4l2 video sensor device and DRM framework in dtssw.multimedia3-21/+380
Signed-off-by: sw.multimedia <sw.multimedia@starfivetech.com> Signed-off-by: andy.hu <andy.hu@starfivetech.com> Signed-off-by: david.li <david.li@starfivetech.com> Signed-off-by: keithzhao <keith.zhao@starfivetech.com> Signed-off-by: Curry Zhang <curry.zhang@starfivetech.com>
2021-09-29starfive: dtsi fix for dma2psw.multimedia1-0/+1
2021-09-29starfive: Add more audio codecs support in dtssw.multimedia6-0/+128
2021-09-29starfive: add clock info in dts for audiosw.multimedia2-0/+154
2021-09-29starfive: add i2c dev info in dts for audiosw.multimedia1-6/+30
2021-09-29starfive: fix dts(linux)TekkamanV1-4/+11
1, ccache 2, mmc This patch adds the necessary info for mmc driver: bus-width = <4>; max-frequency = <?0000000>; 3, uart0(console) 4, SPI Nor Flash 5, Switch dtb to linux dts
2021-09-29starfive: Porting jh7100-beaglev-starlight.dts from linuxTekkamanV4-0/+1105
https://github.com/starfive-tech/linux/tree/beaglev
2021-09-29starfive: Add JH7100 supportTekkamanV7-0/+1739
This patch adds StarFive JH7100 main support, including Starlight and EVB support, ported from StarFive HiFive_U-Boot REPO. The original authors are bo.li <bo.li@starfivetech.com> Chenjieqin <Jessica.Chen@starfivetech.com> Huan.Feng <huan.feng@starfivetech.com> jack.zhu <jack.zhu@starfivetech.com> Jianlong Huang <jianlong.huang@starfivetech.com> ke.zhu <ke.zhu@starfivetech.com> Micheal Zhu <michael.zhu@starfivetech.com> Samin Guo <samin.guo@starfivetech.com> yanhong.wang <yanhong.wang@starfivetech.com> yiming.li <yiming.li@starfivetech.com> Note: 1, disable BTRFS(will trigger a link error with *some* RV64 GCC) But RV64 GCC on Fedora works well with enabling BTRFS. BTRFS will select ZSTD which will trigger a link error with *some* RV64 GCC: --- riscv64-unknown-linux-gnu-ld.bfd: /usr/lib/gcc/riscv64-unknown-linux-gnu/11.2.0/libgcc.a(_clzsi2.o): can't link double-float modules with soft-float modules riscv64-unknown-linux-gnu-ld.bfd: failed to merge target specific data of file /usr/lib/gcc/riscv64-unknown-linux-gnu/11.2.0/libgcc.a(_clzsi2.o) riscv64-unknown-linux-gnu-ld.bfd: /usr/lib/gcc/riscv64-unknown-linux-gnu/11.2.0/libgcc.a(_clz.o): can't link double-float modules with soft-float modules riscv64-unknown-linux-gnu-ld.bfd: failed to merge target specific data of file /usr/lib/gcc/riscv64-unknown-linux-gnu/11.2.0/libgcc.a(_clz.o) make: *** [Makefile:1787: u-boot] Error 1 --- 2, enable OF_SEPARATE: This is required so that openSBI can add itself to /reserved-memory, and let EFI know about it. By Andreas Schwab <schwab@suse.de> 3, Set default fdtfile name By Andreas Schwab <schwab@suse.de>
2021-07-21board: sifive: drop stuff related to unmatched revision 1Zong Li4-1501/+1
This patch reverts the following commits: - 4b4159d0f3 ("riscv: dts: add dts for unmatched rev1") - ffe9a394df ("board: sifive: support spl multi-dtb on unmatched board") We won't plan to support unmatched that the revision below 3 in u-boot, so they can be dropped because they might be useless. Changed in v2: - rebase codebase to the latest master branch Signed-off-by: Zong Li <zong.li@sifive.com> Suggested-by: David Abdurachmanov <david.abdurachmanov@sifive.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-07-07riscv: dts: add OpenPiton RISC-V board dts supportTianrui Wei1-2/+2
Previous device tree for OpenPiton emits a warning during compilation. This commit fixes the previous warning adds dts to the OpenPiton RISC-V board and added the device tree to MAINTAINER file. Signed-off-by: Tianrui Wei <tianrui-wei@outlook.com> Reported-by: Tom Rini <trini@konsulko.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-07-06riscv: dts: add dts for unmatched rev1Zong Li4-1/+1501
The difference between unmatched rev3 and rev1 is DDR timing, the rev3 uses 1866 MT/s for 16GiB, and rev1 uses 2133 MT/s for 8GiB. Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-07-06riscv: sifive: fu740: Support i2c in splZong Li1-0/+4
Enable SPL_I2C_SUPPORT for fu740, and add 'u-boot,dm-spl' property in i2c node. Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-07-06board: riscv: add openpiton-riscv64 SoC supportTianrui Wei2-0/+154
This patch adds openpiton-riscv64 SOC support. In particular, this board supports a standard bootflow through zsbl->u-boot SPL-> opensbi->u-boot proper->Linux. There are separate defconfigs for building u-boot SPL and u-boot proper Signed-off-by: Tianrui Wei <tianrui-wei@outlook.com> Signed-off-by: Jonathan Balkind <jbalkind@ucsb.edu> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-06-28Merge tag 'v2021.07-rc5' into nextTom Rini3-7/+61
Prepare v2021.07-rc5 # gpg: Signature made Mon 28 Jun 2021 03:39:36 PM EDT # gpg: using RSA key 1A3C7F70E08FAB1707809BBF147C39FF9634B72C # gpg: Good signature from "Thomas Rini <trini@konsulko.com>" [ultimate] # Conflicts: # configs/am64x_evm_r5_defconfig
2021-06-17k210: dts: Set PLL1 to the same rate as PLL0Sean Anderson1-0/+2
Linux has had some stability issues when using AISRAM with a different frequency from SRAM. Mirror their change here now that we relocate into AISRAM. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-06-17riscv: ae350: dts: Add missing "u-boot, dm-spl" for SPL configBin Meng3-0/+54
At present the AE350 SPL defconfig is using OF_PRIOR_STAGE. The intention was to use gdb to load device tree before running U-Boot SPL/proper from RAM. When we switch to OF_SEPARATE we will have to use our own DT but without "u-boot,dm-spl" in several essential nodes, SPL does not boot. Let's add all the required "u-boot,dm-spl" for SPL config. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
2021-06-17riscv: ae350: dts: Fix #interrupt-cells for plic0 in 32-bitBin Meng1-1/+1
All the device nodes that refer to plic0 as their interrupt parent have 2 cells encoded in their interrupts property, but plic0 only provides 1 cell in #interrupt-cells which is incorrect. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-06-17riscv: ae350: dts: Remove the unnecessary #address-cells in plic nodesBin Meng2-4/+0
PLIC nodes don't have child nodes, so #address-cells is not needed. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-06-17riscv: ae350: dts: Remove the unnecessary space in bootargsBin Meng2-2/+2
There are two spaces before "debug' in bootargs. Drop one. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-06-17riscv: ae350: dts: Add SPDX license headerBin Meng2-0/+4
The SPDX license header is currently missing. Add one. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
2021-05-31riscv: dts: add SiFive Unmatched board supportGreen Wan4-0/+1790
Add dts files for SiFive Unmatched board. Signed-off-by: Green Wan <green.wan@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
2021-05-31riscv: dts: add fu740 supportGreen Wan2-0/+434
Add dts support for fu740. The HiFive Unmatched support is based on fu740 cpu and drivers in following patch set. Signed-off-by: Green Wan <green.wan@sifive.com> [greentime.hu: set fu740 speed to 1.2GHz] Signed-off-by: Greentime Hu <greentime.hu@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
2021-05-19riscv: ae350: Switch to use binman to generate u-boot.itbBin Meng2-0/+4
Use the new BINMAN_STANDALONE_FDT option for AE350 based SPL defconfigs, so that binman is now used to generate u-boot.itb. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com>
2021-05-19riscv: qemu: Switch to use binman to generate u-boot.itbBin Meng3-0/+17
By utilizing the newly introduced BINMAN_STANDALONE_FDT option, along with a new dedicated device tree source file for the QEMU virt target used for binman only, we can now use binman to generate u-boot.itb. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-05-19riscv: dts: Sort build targets in alphabetical orderBin Meng1-1/+1
Sort the RISC-V DTS build targets by their Kconfig target names in alphabetical order. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-05-19riscv: sifive: unleashed: Switch to use binman to generate u-boot.itbBin Meng2-0/+71
At present SiFive Unleashed board uses the Makefile to create the FIT, using USE_SPL_FIT_GENERATOR, which is deprecated as per the Makefile warning. Update to use binman instead. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-05-14riscv: Don't reserve AI ram in k210 dtsSean Anderson1-12/+0
It is no longer necessary to disallow ai ram, since it is enabled by the sram driver. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2021-05-14riscv: k210: Use AI as the parent clock of aisram, not PLL1Sean Anderson1-1/+1
Testing showed that disabling AI while leaving PLL1 enabled disabled the aisram. This suggests that AI is a more appropriate clock for that ram bank. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2021-05-14riscv: k210: Rename airam to aisramSean Anderson1-2/+2
This is more consistent with the naming of other ram banks, and matches what Linux is doing. Reported-by: Damien Le Moal <Damien.LeMoal@wdc.com> Signed-off-by: Sean Anderson <seanga2@gmail.com>
2021-05-14riscv: Enable some devices pre-relocationSean Anderson1-0/+4
These devices are necessary for the clock driver, which is required by the sram driver, to run pre-relocation. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2021-04-08riscv: dts: mpfs-icicle-kit: Drop 'clock-frequency' in the uart nodesBin Meng1-4/+0
The uart nodes already provide <clocks> property for the driver to dynamically calculate the correct clock frequency. There is no need to keep the hard-coded <clock-frequency> property. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
2021-04-08riscv: sifive: Rename fu540 board to unleashedBin Meng1-1/+1
In preparation to add SiFive Unmatched board support, let's rename the existing fu540 board to unleashed. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-04-08riscv: Add watchdog bindings for the k210Sean Anderson1-1/+0
This adds the necessary bindings. Most of them are already there. Signed-off-by: Sean Anderson <seanga2@gmail.com> Acked-by: Rick Chen <rick@andestech.com>
2021-02-25riscv: k210: Enable QSPI for spi3Sean Anderson1-0/+2
This device has four IOs connected to the SPI flash. Add the appropriate bindings. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Leo Liang <ycliang@andestech.com>
2021-01-18riscv: dts: Add device tree for Microchip Icicle KitPadmarao Begari3-0/+436
Add device tree for Microchip PolarFire SoC Icicle Kit. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-12-18riscv: Add device tree bindings for SPISean Anderson2-1/+47
This patch adds bindings for the MMC slot and SPI flash on the Sipeed Maix Bit. Signed-off-by: Sean Anderson <seanga2@gmail.com> Acked-by: Rick Chen <rick@andestech.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-12-18spi: dw: Add SoC-specific compatible stringsSean Anderson1-5/+8
This adds SoC-specific compatible strings to all users of the designware spi device. This will allow for the correct driver to be selected for each device. Where it is publicly documented, a compatible string for the specific device version has also been added. Devices without publicly-documented device versions include MSCC SoCs, and Arc Socs. All compatible strings except those for SoCFPGAs and some of the versioned strings have been taken from Linux. Since SSI_MAX_XFER_SIZE is determined at runtime, this is not strictly necessary. However, it is a good cleanup and brings things closer to Linux. Signed-off-by: Sean Anderson <seanga2@gmail.com> Tested-by Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-10-26riscv: fu540: dts: Correct reg size of clint nodePragnesh Patel1-1/+1
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Rick Chen <rick@andestech.com>
2020-10-26riscv: k210: Reduce DMA block sizeSean Anderson1-2/+2
Although the max DMA size supported by the hardware register is 22 bits (or 4M), the Linux driver for this device only supports transfers of up to 2M. On a device with 8M total memory, I don't think it will make too much of a difference. Reported-by: Damien Le Moal <Damien.LeMoal@wdc.com> Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
2020-10-08riscv: add DT binding for BOOT button on Maix boardHeinrich Schuchardt1-0/+11
Add a device tree binding for the BOOT button on the Maix board. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Sean Anderson <seanga2@gmail.com> Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
2020-10-08riscv: Add pinmux and gpio bindings for Kendryte K210Sean Anderson2-0/+116
This patch adds the necessary device tree bindings. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Rick Chen <rick@andestech.com>
2020-09-30riscv: Update SiFive device tree for new CLINT driverSean Anderson2-2/+10
We currently do this in a u-boot specific dts, but hopefully we can get these bindings added in Linux in the future. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@openfive.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
generated by cgit v1.2.3 (git 2.39.0) at 2024-09-30 12:03:40 +0300