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2023-04-10dts: pmu: remove pmu dts stall cycles config.Minda Chen1-5/+2
class 8 and class9 cpu stall cycles hwcounter is not supported in U74. delete the configuration. Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
2023-04-04riscv: dts: jh7110: Add L2 pretcher configurationSamin Guo1-0/+10
Add L2 pretcher configuration for starfive jh7110 SoC. Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2023-03-28riscv: dts: starfive: Add gpio-controller for the gpio nodeHal Feng1-0/+2
Add gpio-controller for node gpio and gpioa. Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2023-03-17riscv: support building double-float modulesHeinrich Schuchardt2-3/+27
The riscv32 toolchain for GCC-12 provided by kernel.org contains libgcc.a compiled for double-float. To link to it we have to adjust how we build U-Boot. As U-Boot actually does not use floating point at all this should not make a significant difference for the produced binaries. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-03-17riscv: Fix build against binutils 2.38Alexandre Ghiti1-1/+10
The following description is copied from the equivalent patch for the Linux Kernel proposed by Aurelien Jarno: >From version 2.38, binutils default to ISA spec version 20191213. This means that the csr read/write (csrr*/csrw*) instructions and fence.i instruction has separated from the `I` extension, become two standalone extensions: Zicsr and Zifencei. As the kernel uses those instruction, this causes the following build failure: arch/riscv/cpu/mtrap.S: Assembler messages: arch/riscv/cpu/mtrap.S:65: Error: unrecognized opcode `csrr a0,scause' arch/riscv/cpu/mtrap.S:66: Error: unrecognized opcode `csrr a1,sepc' arch/riscv/cpu/mtrap.S:67: Error: unrecognized opcode `csrr a2,stval' arch/riscv/cpu/mtrap.S:70: Error: unrecognized opcode `csrw sepc,a0' Signed-off-by: Alexandre Ghiti <alexandre.ghiti@canonical.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Tested-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Christian Stewart <christian@paral.in> Reviewed-by: Rick Chen <rick@andestech.com>
2023-03-08riscv: dts: enable hdmi dts config in ubootkeith.zhao2-46/+13
hdmi can show a bitmap logo while uboot start and the default resolution is 1920x1080@60fps Signed-off-by: keith.zhao<keith.zhao@statfivetech.com>
2023-02-22riscv: dts: starfive: Enable PCIe host controllerMason Huo2-12/+114
Enable and add pinctrl configuration for PCIe host controller. Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
2023-02-21riscv:uboot:cache driverkeith.zhao1-1/+1
cache driver enabled by config STARFIVE_JH7110_L2CC_FLUSH if not , there is a dump on vf2 Signed-off-by:keith.zhao<keith.zhao@statfivetech.com>
2023-02-17dts:riscv:jh7110: add mipi driver nodekeith.zhao2-94/+329
update dts node to support vout mipi driver Signed-off-by:keith.zhao<keith.zhao@statfivetech.com>
2023-02-17riscv:cache:jh7110: add cache driverkeith.zhao3-0/+66
support flush_dcache_range interface STARFIVE_JH7110_L2CC_FLUSH Signed-off-by:keith.zhao<keith.zhao@statfivetech.com>
2023-02-03Merge branch 'CR_3238_Reserved_memory_mason.huo' into 'jh7110-master'andy.hu1-1/+11
CR_3238 exclude opensbi memory range in device tree See merge request sdk/u-boot!27
2023-02-03exclude opensbi memory range in device treeFelix Moessbauer1-1/+11
This patch explicitly excludes the memory range of the OpenSBI in the built-in device tree. When booting EFI, the efi loader has to know about that zone before loading the device tree for Linux, otherwise it tries to access 0x40000000, leading to an access violation. Signed-off-by: Felix Moessbauer <felix.moessbauer@siemens.com>
2023-02-02sysreset: provide SBI based sysreset driverHeinrich Schuchardt3-1/+25
Provide sysreset driver using the SBI system reset extension. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Samuel Holland <samuel@sholland.org>
2023-02-02riscv: add missing SBI extension definitionsHeinrich Schuchardt1-2/+37
Add the System Reset Extension and the Hart State Management Extension definitions. Add missing RFENCE Extension enum values. The SBI 0.1 extension constants are needed for the sbi command. Remove an #ifdef. Cf. https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.adoc Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-01-09dts: add boot-hart-id property in dtsminda.chen1-0/+1
boot-hart-id is used by opensbi. Signed-off-by: minda.chen <minda.chen@starfivetech.com>
2023-01-06Merge branch 'CR_3049_Hibernation_mason.huo' into 'jh7110-master'andy.hu2-0/+20
CR_3049 dts: add i2c5 and attach pmic configuration See merge request sdk/u-boot!22
2023-01-06Merge branch 'CR_2708_VOUTCLK_yanhong.wang' into 'jh7110-master'andy.hu1-1/+0
CR 2708 clk:starfive: Add vout clock driver for StarFive JH7110 See merge request sdk/u-boot!23
2023-01-05clk:starfive: Add vout clock driver for StarFive JH7110Yanhong Wang1-1/+0
Add vout clock driver for StarFive JH7110 Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
2023-01-05dts: add i2c5 and attach pmic configurationminda.chen2-0/+20
i2c5 and pmic is used by opensbi power management ops. Signed-off-by: minda.chen <minda.chen@starfivetech.com>
2023-01-03dts: pmu : add riscv pmu dts configminda.chen1-0/+46
add 7110 performance monitor for perf use Signed-off-by: minda.chen <minda.chen@starfivetech.com>
2022-12-14board:starfive:jh7110: default cpufreq is 1000Mhz.Samin Guo1-1/+1
The frequency of pll0 is set to 1000Mhz in the bootrom Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2022-11-23dts:starfive:Add pinctrl configJianlong Huang2-7/+59
Add pinctrl config about usb/sdio0 Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
2022-11-01board:starfive:evb: add get_chip_typeSamin Guo1-0/+2
Read the chip model from the rgpio3 and setenv "chip_vision" 1: jh7110B 0: JH7110A defalut: JH7110A Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2022-11-01board:starfive:evb: add jh7110_gmac_sel_tx_to_rgmiiSamin Guo1-0/+8
JH7110B needs switch gmac0/1 tx to rgmii phy. Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2022-11-01dts:starfive:jh7110: set gmac phy tx_inverted for JH7110A/B.Samin Guo1-1/+11
JH7110B requires tx_inverted_10/100/1000 configuration, and different parameters may be required in 10M/100M/1000M mode. This parameter supports JH7110B+YT8531PHY by default. Other boards can modify the parameters of the tx_inverted_10/100/1000 to obtain support. If you do not configure tx_inverted_10/100/1000 in dts, the default is 0. Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2022-10-18riscv: dts: jh7110: Add reset property to DDR control nodeYan Hong Wang1-1/+5
Add reset property configuration to DDR control device tree node. Signed-off-by: Yan Hong Wang <yanhongwang@linux.starfivetech.com>
2022-10-18arch: riscv: jh7110: add pll clk configuration for jh7110Yan Hong Wang4-18/+416
Add common interface to set and get pll clk information for jh7110 soc. Signed-off-by: Yan Hong Wang <yanhong.wang@starfivetech.com>
2022-10-18riscv:dts:starfive-jh7110: modify Model and riscv,isa infoyanhong.wang2-6/+6
Change Model to "StarFive JH7110 EVB", and change riscv,isa to "rv64imafdcbsux" Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18board:starfive:evb: update uart3-uart5 resetsyanhong.wang1-6/+12
Add SPL_DM_RESET to defconfig, and update uart3-uart5 reset for StarFive JH7110 SoC. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18SPL:starfive-jh7110: Modify the default division factor of sdcard clkyanhong.wang1-0/+4
Modify the default division factor of sdcard clk to 4. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18board:starfive:evb: add usb init configyanhong.wang1-0/+18
Add usb init config for starfive EVB board. Default set to USB2.0 Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18clk:starfive-jh7110: Update pll0/pll1/pll2 clkyanhong.wang1-18/+0
Remove pll0/pll1/pll2 clk define from jh7110_clk.dts to clk-jh7110.c Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18spl: satrfive: bus_root switch to pll2.samin1-5/+0
High-speed emmc/sdio support Signed-off-by: samin <samin.guo@starfivetech.com>
2022-10-18board:starfive:evb: modify the GPIO configuration for sd moduleyanhong.wang1-0/+5
Modify the GPIO configuration for sd&emmc module, switch the clk of sd&emmc to high frequency Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18riscv:dts:starfive-jh7110: Modify sd node configurationyanhong.wang4-38/+7
Modify SD&EMMC node configuration on Starfive EVB board. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18SPL:riscv:starfive-jh7110: Adjust CPU working frequencyyanhong.wang2-1/+18
Adjust CPU working frequency from 1G to 1.25G for starfive EVB board. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18riscv:dts:starfive-jh7110: add ethernet-phy delay_chain configyanhong.wang2-4/+17
Add ethernet-phy delay_chain configuration for gmac1 on starfive EVB board. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18riscv:starfive-jh7110: clear L2 LIM memoryyanhong.wang1-0/+14
Clear L2 LIM memory on StarFive JH7110, avoid some unexpect exception.
2022-10-18riscv:dts:starfive-jh7110: add ddr device nodeyanhong.wang1-0/+7
Add ddr device node for JH7110. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18board:starfive: add clk inityanhong.wang1-5/+27
Add clk init for ddr on JH7110 board Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18clk:starfive-jh7110: Update pll0/pll1/pll2 clkyanhong.wang2-3/+22
Add JH7110_GMAC0_GTXC clk register and remove pll0/pll1/pll2 clk define from clk-jh7110.c to jh7110_clk.dts Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18GPIO:Starfive-jh7110: Add macro definitionyanhong.wang1-0/+21
Add macro definition of GPIO Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18board:starfive: add starfive evb board supportyanhong.wang5-0/+153
Add board support for StarFive EVB. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18riscv:dts: update clk&reset propertiesyanhong.wang2-157/+443
Synchronize the kernel dts file Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18riscv:dts: update clk&reset propertiesyanhong.wang2-53/+182
Synchronize the kernel dts file Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18board:starfive: add rtc timer inityanhong.wang1-0/+16
The rtc timer is used early in kernel, but the clk&reset driver is not ready,so some clk&reset init is placed here. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18board:starfive: add starfive visionfive board supportyanhong.wang2-0/+49
Add board support for StarFive VisionFive. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18riscv:dts: add jh7110 supportyanhong.wang6-0/+1341
Add dts support for jh7110. The starfive visionfive support is based on jh7110 soc. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18riscv:soc:jh7110: Add support jh7110 soc.yanhong.wang7-0/+180
Add StarFive JH7110 soc to support RISC-V arch Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18GPIO:Starfive-jh7110: Add GPIO driver for JH7110yanhong.wang1-0/+53
Support for GPIO controller on starfive JH7110 SoCs. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
generated by cgit v1.2.3 (git 2.39.0) at 2024-08-09 15:35:58 +0300