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starfive-tech/u-boot.git
Fedora_JH7100_2021.04
Fedora_JH7100_2021.07
Fedora_JH7100_upstream
Fedora_JH7100_upstream_devel
JH7100_Multimedia_V0.1.0
JH7100_VisionFive_OH_dev
JH7100_VisionFive_devel
JH7100_starlight_multimedia
JH7100_upstream
JH7100_upstream_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_devel-v3.9.3
dubhe_fpga_dev_v2023.10
master
rtthread_AMP
visionfive_devel
StarFive Tech U-Boot for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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riscv
Age
Commit message (
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Author
Files
Lines
2020-09-30
riscv: Add some comments to start.S
Sean Anderson
1
-2
/
+17
2020-09-30
riscv: Ensure gp is NULL or points to valid data
Sean Anderson
2
-4
/
+27
2020-09-30
riscv: Consolidate fences into AMOs for available_harts_lock
Sean Anderson
1
-6
/
+3
2020-09-30
riscv: Clear pending IPIs on initialization
Sean Anderson
1
-0
/
+20
2020-09-30
riscv: Use a valid bit to ignore already-pending IPIs
Sean Anderson
2
-2
/
+21
2020-09-30
riscv: Match memory barriers between send_ipi_many and handle_ipi
Sean Anderson
1
-0
/
+2
2020-09-30
Revert "riscv: Clear pending interrupts before enabling IPIs"
Sean Anderson
1
-2
/
+0
2020-09-30
riscv: Update SiFive device tree for new CLINT driver
Sean Anderson
2
-2
/
+10
2020-09-30
riscv: Update Kendryte device tree for new CLINT driver
Sean Anderson
1
-3
/
+4
2020-09-30
riscv: Rework Sifive CLINT as UCLASS_TIMER driver
Sean Anderson
2
-32
/
+34
2020-09-30
riscv: Clean up initialization in Andes PLIC
Sean Anderson
1
-33
/
+25
2020-09-30
riscv: Rework Andes PLMT as a UCLASS_TIMER driver
Sean Anderson
4
-32
/
+23
2020-09-30
riscv: Rework riscv timer driver to only support S-mode
Sean Anderson
6
-50
/
+3
2020-09-22
fdtdec: optionally add property no-map to created reserved memory node
Etienne Carriere
1
-1
/
+1
2020-09-15
riscv: define function set_gd()
Heinrich Schuchardt
1
-0
/
+9
2020-08-25
cmd: provide command sbi
Heinrich Schuchardt
2
-0
/
+38
2020-08-25
riscv: fix building with CONFIG_SPL_SMP=n
Heinrich Schuchardt
1
-1
/
+1
2020-08-25
riscv: fu540: Use correct API to get L2 cache controller base address
Bin Meng
1
-1
/
+2
2020-08-14
riscv: additional crash information
Heinrich Schuchardt
1
-22
/
+35
2020-08-14
riscv: sifive: fu540: redundant initialization
Heinrich Schuchardt
1
-1
/
+1
2020-08-14
riscv: remove redundant logical constraint.
Heinrich Schuchardt
1
-1
/
+1
2020-08-14
riscv: sifive/fu540: kconfig: Move FU540 driver related options to the SoC level
Bin Meng
1
-0
/
+22
2020-08-14
riscv: sifive/fu540: spl: Rename soc_spl_init()
Bin Meng
2
-2
/
+2
2020-08-14
riscv: Call spl_board_init_f() in the generic SPL board_init_f()
Bin Meng
2
-0
/
+16
2020-08-04
sifive: reset: add DM based reset driver for SiFive SoC's
Sagar Shrikant Kadam
1
-0
/
+13
2020-08-04
fu540: dtsi: add reset producer and consumer entries
Sagar Shrikant Kadam
1
-0
/
+12
2020-07-24
riscv: dts: hifive-unleashed-a00: Make memory node available to SPL
Bin Meng
1
-0
/
+4
2020-07-24
riscv: Fix linking error when building u-boot-spl with no SMP support
Leo Yu-Chi Liang
1
-0
/
+2
2020-07-24
Revert "riscv: Allow use of reset drivers"
Bin Meng
1
-2
/
+0
2020-07-24
env: Enable SPI flash env for SiFive FU540
Jagan Teki
1
-0
/
+13
2020-07-24
sifive: fu540: Add Booting from SPI
Jagan Teki
1
-0
/
+12
2020-07-24
riscv: Make SiFive HiFive Unleashed board boot again
Bin Meng
2
-5
/
+13
2020-07-06
Merge branch 'next'
Tom Rini
16
-103
/
+801
2020-07-03
riscv: use log functions in fdt_fixup
Heinrich Schuchardt
1
-6
/
+8
2020-07-03
riscv: sifive: fu540: enable all cache ways from U-Boot proper
Pragnesh Patel
4
-0
/
+72
2020-07-03
riscv: Use optimized version of fdtdec_get_addr_size_no_parent
Atish Patra
1
-3
/
+3
2020-07-03
riscv: Do not return error if reserved node already exists
Atish Patra
1
-1
/
+1
2020-07-03
riscv: Do not build reset.c if SYSRESET is on
Bin Meng
1
-0
/
+2
2020-07-02
riscv: Enable CONFIG_OF_BOARD_FIXUP by default for OF_SEPARATE
Bin Meng
1
-0
/
+3
2020-07-02
riscv: Expand the DT size before copy reserved memory node
Bin Meng
1
-0
/
+12
2020-07-02
riscv: Avoid the reserved memory fixup if src and dst point to the same place
Bin Meng
1
-4
/
+8
2020-07-02
riscv: fu540: dts: Correct reg size of otp and dmc nodes
Bin Meng
1
-2
/
+2
2020-07-02
riscv: fu540: dts: Remove the unnecessary space in the cpu2_intc node
Bin Meng
1
-1
/
+1
2020-07-01
riscv: dts: hifive-unleashed-a00: add cpu aliases
Sagar Shrikant Kadam
1
-0
/
+4
2020-07-01
riscv: Add Sipeed Maix support
Sean Anderson
1
-0
/
+4
2020-07-01
riscv: Add device tree for K210 and Sipeed Maix BitM
Sean Anderson
3
-0
/
+642
2020-07-01
riscv: Allow use of reset drivers
Sean Anderson
1
-0
/
+2
2020-07-01
riscv: Add option to support RISC-V privileged spec 1.9
Sean Anderson
3
-0
/
+59
2020-07-01
riscv: Clean up IPI initialization code
Sean Anderson
6
-86
/
+84
2020-07-01
riscv: Clear pending interrupts before enabling IPIs
Sean Anderson
1
-0
/
+2
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