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2022-10-18riscv:dts:starfive-jh7110: modify Model and riscv,isa infoyanhong.wang2-6/+6
2022-10-18board:starfive:evb: update uart3-uart5 resetsyanhong.wang1-6/+12
2022-10-18SPL:starfive-jh7110: Modify the default division factor of sdcard clkyanhong.wang1-0/+4
2022-10-18board:starfive:evb: add usb init configyanhong.wang1-0/+18
2022-10-18clk:starfive-jh7110: Update pll0/pll1/pll2 clkyanhong.wang1-18/+0
2022-10-18spl: satrfive: bus_root switch to pll2.samin1-5/+0
2022-10-18board:starfive:evb: modify the GPIO configuration for sd moduleyanhong.wang1-0/+5
2022-10-18riscv:dts:starfive-jh7110: Modify sd node configurationyanhong.wang4-38/+7
2022-10-18SPL:riscv:starfive-jh7110: Adjust CPU working frequencyyanhong.wang2-1/+18
2022-10-18riscv:dts:starfive-jh7110: add ethernet-phy delay_chain configyanhong.wang2-4/+17
2022-10-18riscv:starfive-jh7110: clear L2 LIM memoryyanhong.wang1-0/+14
2022-10-18riscv:dts:starfive-jh7110: add ddr device nodeyanhong.wang1-0/+7
2022-10-18board:starfive: add clk inityanhong.wang1-5/+27
2022-10-18clk:starfive-jh7110: Update pll0/pll1/pll2 clkyanhong.wang2-3/+22
2022-10-18GPIO:Starfive-jh7110: Add macro definitionyanhong.wang1-0/+21
2022-10-18board:starfive: add starfive evb board supportyanhong.wang5-0/+153
2022-10-18riscv:dts: update clk&reset propertiesyanhong.wang2-157/+443
2022-10-18riscv:dts: update clk&reset propertiesyanhong.wang2-53/+182
2022-10-18board:starfive: add rtc timer inityanhong.wang1-0/+16
2022-10-18board:starfive: add starfive visionfive board supportyanhong.wang2-0/+49
2022-10-18riscv:dts: add jh7110 supportyanhong.wang6-0/+1341
2022-10-18riscv:soc:jh7110: Add support jh7110 soc.yanhong.wang7-0/+180
2022-10-18GPIO:Starfive-jh7110: Add GPIO driver for JH7110yanhong.wang1-0/+53
2021-09-07riscv: lib: modify the indentZong Li1-1/+1
2021-09-07board: sifive: use ccache driver instead of helper functionZong Li8-140/+4
2021-09-07riscv: lib: implement enable_caches for sifive cacheZong Li3-0/+33
2021-09-07common: board_r: support enable_caches for RISC-VZong Li1-0/+4
2021-09-07riscv: show code leading to exceptionHeinrich Schuchardt1-0/+33
2021-08-17riscv: cpu: fu740: Fix typo of dateZong Li1-1/+1
2021-08-14efi_loader: add Linux magic to RISC-V crt0Heinrich Schuchardt1-2/+5
2021-07-28i2c: Rename SPL/TPL_I2C_SUPPORT to I2CSimon Glass1-1/+1
2021-07-21board: sifive: drop stuff related to unmatched revision 1Zong Li4-1501/+1
2021-07-21riscv: booti: do not force relocation if force_reloc is not setVitaly Wool1-1/+6
2021-07-07riscv: dts: add OpenPiton RISC-V board dts supportTianrui Wei1-2/+2
2021-07-06riscv: dts: add dts for unmatched rev1Zong Li4-1/+1501
2021-07-06board: sifive: Add an interface to get PCB revisionZong Li1-0/+15
2021-07-06riscv: sifive: fu740: Support i2c in splZong Li2-0/+5
2021-07-06riscv: sifive: fu740: kconfig: Enable support for Opencores I2C controllerZong Li1-0/+2
2021-07-06board: riscv: add openpiton-riscv64 SoC supportTianrui Wei3-0/+158
2021-06-28Merge tag 'v2021.07-rc5' into nextTom Rini4-8/+64
2021-06-17k210: dts: Set PLL1 to the same rate as PLL0Sean Anderson1-0/+2
2021-06-17riscv: andes_plic: Fix riscv_get_ipi() maskBin Meng1-1/+3
2021-06-17riscv: ae350: dts: Add missing "u-boot, dm-spl" for SPL configBin Meng3-0/+54
2021-06-17riscv: ae350: dts: Fix #interrupt-cells for plic0 in 32-bitBin Meng1-1/+1
2021-06-17riscv: ae350: dts: Remove the unnecessary #address-cells in plic nodesBin Meng2-4/+0
2021-06-17riscv: ae350: dts: Remove the unnecessary space in bootargsBin Meng2-2/+2
2021-06-17riscv: ae350: dts: Add SPDX license headerBin Meng2-0/+4
2021-05-31riscv: cpu: fu740: clear feature disable CSRGreen Wan1-0/+15
2021-05-31board: sifive: add HiFive Unmatched board supportGreen Wan1-0/+4
2021-05-31riscv: dts: add SiFive Unmatched board supportGreen Wan4-0/+1790