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2023-01-06Merge branch 'CR_2708_VOUTCLK_yanhong.wang' into 'jh7110-master'andy.hu1-1/+0
CR 2708 clk:starfive: Add vout clock driver for StarFive JH7110 See merge request sdk/u-boot!23
2023-01-05clk:starfive: Add vout clock driver for StarFive JH7110Yanhong Wang1-1/+0
Add vout clock driver for StarFive JH7110 Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
2023-01-03dts: pmu : add riscv pmu dts configminda.chen1-0/+46
add 7110 performance monitor for perf use Signed-off-by: minda.chen <minda.chen@starfivetech.com>
2022-12-14board:starfive:jh7110: default cpufreq is 1000Mhz.Samin Guo1-1/+1
The frequency of pll0 is set to 1000Mhz in the bootrom Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2022-11-23dts:starfive:Add pinctrl configJianlong Huang2-7/+59
Add pinctrl config about usb/sdio0 Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
2022-11-01board:starfive:evb: add get_chip_typeSamin Guo1-0/+2
Read the chip model from the rgpio3 and setenv "chip_vision" 1: jh7110B 0: JH7110A defalut: JH7110A Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2022-11-01board:starfive:evb: add jh7110_gmac_sel_tx_to_rgmiiSamin Guo1-0/+8
JH7110B needs switch gmac0/1 tx to rgmii phy. Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2022-11-01dts:starfive:jh7110: set gmac phy tx_inverted for JH7110A/B.Samin Guo1-1/+11
JH7110B requires tx_inverted_10/100/1000 configuration, and different parameters may be required in 10M/100M/1000M mode. This parameter supports JH7110B+YT8531PHY by default. Other boards can modify the parameters of the tx_inverted_10/100/1000 to obtain support. If you do not configure tx_inverted_10/100/1000 in dts, the default is 0. Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2022-10-18riscv: dts: jh7110: Add reset property to DDR control nodeYan Hong Wang1-1/+5
Add reset property configuration to DDR control device tree node. Signed-off-by: Yan Hong Wang <yanhongwang@linux.starfivetech.com>
2022-10-18arch: riscv: jh7110: add pll clk configuration for jh7110Yan Hong Wang4-18/+416
Add common interface to set and get pll clk information for jh7110 soc. Signed-off-by: Yan Hong Wang <yanhong.wang@starfivetech.com>
2022-10-18riscv:dts:starfive-jh7110: modify Model and riscv,isa infoyanhong.wang2-6/+6
Change Model to "StarFive JH7110 EVB", and change riscv,isa to "rv64imafdcbsux" Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18board:starfive:evb: update uart3-uart5 resetsyanhong.wang1-6/+12
Add SPL_DM_RESET to defconfig, and update uart3-uart5 reset for StarFive JH7110 SoC. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18SPL:starfive-jh7110: Modify the default division factor of sdcard clkyanhong.wang1-0/+4
Modify the default division factor of sdcard clk to 4. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18board:starfive:evb: add usb init configyanhong.wang1-0/+18
Add usb init config for starfive EVB board. Default set to USB2.0 Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18clk:starfive-jh7110: Update pll0/pll1/pll2 clkyanhong.wang1-18/+0
Remove pll0/pll1/pll2 clk define from jh7110_clk.dts to clk-jh7110.c Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18spl: satrfive: bus_root switch to pll2.samin1-5/+0
High-speed emmc/sdio support Signed-off-by: samin <samin.guo@starfivetech.com>
2022-10-18board:starfive:evb: modify the GPIO configuration for sd moduleyanhong.wang1-0/+5
Modify the GPIO configuration for sd&emmc module, switch the clk of sd&emmc to high frequency Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18riscv:dts:starfive-jh7110: Modify sd node configurationyanhong.wang4-38/+7
Modify SD&EMMC node configuration on Starfive EVB board. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18SPL:riscv:starfive-jh7110: Adjust CPU working frequencyyanhong.wang2-1/+18
Adjust CPU working frequency from 1G to 1.25G for starfive EVB board. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18riscv:dts:starfive-jh7110: add ethernet-phy delay_chain configyanhong.wang2-4/+17
Add ethernet-phy delay_chain configuration for gmac1 on starfive EVB board. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18riscv:starfive-jh7110: clear L2 LIM memoryyanhong.wang1-0/+14
Clear L2 LIM memory on StarFive JH7110, avoid some unexpect exception.
2022-10-18riscv:dts:starfive-jh7110: add ddr device nodeyanhong.wang1-0/+7
Add ddr device node for JH7110. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18board:starfive: add clk inityanhong.wang1-5/+27
Add clk init for ddr on JH7110 board Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18clk:starfive-jh7110: Update pll0/pll1/pll2 clkyanhong.wang2-3/+22
Add JH7110_GMAC0_GTXC clk register and remove pll0/pll1/pll2 clk define from clk-jh7110.c to jh7110_clk.dts Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18GPIO:Starfive-jh7110: Add macro definitionyanhong.wang1-0/+21
Add macro definition of GPIO Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18board:starfive: add starfive evb board supportyanhong.wang5-0/+153
Add board support for StarFive EVB. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18riscv:dts: update clk&reset propertiesyanhong.wang2-157/+443
Synchronize the kernel dts file Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18riscv:dts: update clk&reset propertiesyanhong.wang2-53/+182
Synchronize the kernel dts file Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18board:starfive: add rtc timer inityanhong.wang1-0/+16
The rtc timer is used early in kernel, but the clk&reset driver is not ready,so some clk&reset init is placed here. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18board:starfive: add starfive visionfive board supportyanhong.wang2-0/+49
Add board support for StarFive VisionFive. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18riscv:dts: add jh7110 supportyanhong.wang6-0/+1341
Add dts support for jh7110. The starfive visionfive support is based on jh7110 soc. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18riscv:soc:jh7110: Add support jh7110 soc.yanhong.wang7-0/+180
Add StarFive JH7110 soc to support RISC-V arch Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18GPIO:Starfive-jh7110: Add GPIO driver for JH7110yanhong.wang1-0/+53
Support for GPIO controller on starfive JH7110 SoCs. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2021-09-07riscv: lib: modify the indentZong Li1-1/+1
We usually use a space in function declaration, rather than a tab. Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
2021-09-07board: sifive: use ccache driver instead of helper functionZong Li8-140/+4
Invokes the common cache_init function to initialize ccache. Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
2021-09-07riscv: lib: implement enable_caches for sifive cacheZong Li3-0/+33
The enable_caches is a generic hook for architecture-implemented, we define this function to enable composable cache of sifive platforms. In sifive_cache, it invokes the generic cache_enable interface of cache uclass to execute the relative implementation in SiFive ccache driver. Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
2021-09-07common: board_r: support enable_caches for RISC-VZong Li1-0/+4
The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
2021-09-07riscv: show code leading to exceptionHeinrich Schuchardt1-0/+33
To make analyzing exceptions easier output the code that leads to it. We already do the same on the ARM platform. Here is an example: => exception ebreak Unhandled exception: Breakpoint EPC: 000000008ff5d50e RA: 000000008ff5d62c TVAL: 0000000000000000 EPC: 000000008020b50e RA: 000000008020b62c reloc adjusted Code: 2785 0693 07a0 dce3 fef6 47a5 d563 00e7 (9002) To disassemble the code we can use the decodecode script: $ echo 'Code: 2785 0693 07a0 dce3 fef6 47a5 d563 00e7 (9002)' | \ CROSS_COMPILE=riscv64-linux-gnu- scripts/decodecode Code: 2785 0693 07a0 dce3 fef6 47a5 d563 00e7 (9002) All code ======== 0: 2785 addiw a5,a5,1 2: 07a00693 li a3,122 6: fef6dce3 bge a3,a5,0xfffffffffffffffe a: 47a5 li a5,9 c: 00e7d563 bge a5,a4,0x16 10:* 9002 ebreak <-- trapping instruction ... Code starting with the faulting instruction =========================================== 0: 9002 ebreak ... As it is not always clear if the first 16 bits are at the start or in the middle of a 32bit instruction it may become necessary to strip the first u16 from the output before calling decodecode to get the correct disassembled code. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Sean Anderson <seanga2@gmail.com>
2021-08-17riscv: cpu: fu740: Fix typo of dateZong Li1-1/+1
Fixed the typo of date of copyright declaration. Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-08-14efi_loader: add Linux magic to RISC-V crt0Heinrich Schuchardt1-2/+5
Add the Linux magic to the EFI file header to allow running our test programs with GRUB's linux command. MajorImageVersion = 1 indicates a kernel that can consume the EFI_LOAD_FILE2_PROTOCOL. This allows to dump the GRUB provided intird with our initrddump.efi tool. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-07-28i2c: Rename SPL/TPL_I2C_SUPPORT to I2CSimon Glass1-1/+1
Rename these options so that CONFIG_IS_ENABLED can be used with them. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
2021-07-21board: sifive: drop stuff related to unmatched revision 1Zong Li4-1501/+1
This patch reverts the following commits: - 4b4159d0f3 ("riscv: dts: add dts for unmatched rev1") - ffe9a394df ("board: sifive: support spl multi-dtb on unmatched board") We won't plan to support unmatched that the revision below 3 in u-boot, so they can be dropped because they might be useless. Changed in v2: - rebase codebase to the latest master branch Signed-off-by: Zong Li <zong.li@sifive.com> Suggested-by: David Abdurachmanov <david.abdurachmanov@sifive.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-07-21riscv: booti: do not force relocation if force_reloc is not setVitaly Wool1-1/+6
If force_reloc flag is not set and booti is called for an address ouside RAM (i. e. QSPI NOR flash), we should honor that and not try to force relocation in a bogus fashion. Signed-off-by: Vitaly Wool <vitaly.wool@konsulko.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-07-07riscv: dts: add OpenPiton RISC-V board dts supportTianrui Wei1-2/+2
Previous device tree for OpenPiton emits a warning during compilation. This commit fixes the previous warning adds dts to the OpenPiton RISC-V board and added the device tree to MAINTAINER file. Signed-off-by: Tianrui Wei <tianrui-wei@outlook.com> Reported-by: Tom Rini <trini@konsulko.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-07-06riscv: dts: add dts for unmatched rev1Zong Li4-1/+1501
The difference between unmatched rev3 and rev1 is DDR timing, the rev3 uses 1866 MT/s for 16GiB, and rev1 uses 2133 MT/s for 8GiB. Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-07-06board: sifive: Add an interface to get PCB revisionZong Li1-0/+15
There are different DDR parameter settings for different board revisions. Add a new interface to get the PCB revision to determine which DT should be selected at runtime. Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-07-06riscv: sifive: fu740: Support i2c in splZong Li2-0/+5
Enable SPL_I2C_SUPPORT for fu740, and add 'u-boot,dm-spl' property in i2c node. Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-07-06riscv: sifive: fu740: kconfig: Enable support for Opencores I2C controllerZong Li1-0/+2
Enable the Opencores I2C controller on FU740 Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-07-06board: riscv: add openpiton-riscv64 SoC supportTianrui Wei3-0/+158
This patch adds openpiton-riscv64 SOC support. In particular, this board supports a standard bootflow through zsbl->u-boot SPL-> opensbi->u-boot proper->Linux. There are separate defconfigs for building u-boot SPL and u-boot proper Signed-off-by: Tianrui Wei <tianrui-wei@outlook.com> Signed-off-by: Jonathan Balkind <jbalkind@ucsb.edu> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-06-28Merge tag 'v2021.07-rc5' into nextTom Rini4-8/+64
Prepare v2021.07-rc5 # gpg: Signature made Mon 28 Jun 2021 03:39:36 PM EDT # gpg: using RSA key 1A3C7F70E08FAB1707809BBF147C39FF9634B72C # gpg: Good signature from "Thomas Rini <trini@konsulko.com>" [ultimate] # Conflicts: # configs/am64x_evm_r5_defconfig
generated by cgit v1.2.3 (git 2.39.0) at 2024-09-05 01:43:28 +0300