starfive-tech/u-boot.git - StarFive Tech U-Boot for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2021-09-23	lmb: riscv: Add arch_lmb_reserve()	Marek Vasut	1	-0/+13
2021-09-16	Merge tag 'v2021.10-rc4' into next	Tom Rini	14	-141/+75
2021-09-07	riscv: lib: modify the indent	Zong Li	1	-1/+1
2021-09-07	board: sifive: use ccache driver instead of helper function	Zong Li	8	-140/+4
2021-09-07	riscv: lib: implement enable_caches for sifive cache	Zong Li	3	-0/+33
2021-09-07	common: board_r: support enable_caches for RISC-V	Zong Li	1	-0/+4
2021-09-07	riscv: show code leading to exception	Heinrich Schuchardt	1	-0/+33
2021-09-01	Kconfig: Remove all default n/no options	Michal Simek	1	-2/+0
2021-09-01	Finish converting CONFIG_SYS_CACHELINE_SIZE to Kconfig	Tom Rini	1	-0/+2
2021-08-17	riscv: cpu: fu740: Fix typo of date	Zong Li	1	-1/+1
2021-08-14	efi_loader: add Linux magic to RISC-V crt0	Heinrich Schuchardt	1	-2/+5
2021-07-28	i2c: Rename SPL/TPL_I2C_SUPPORT to I2C	Simon Glass	1	-1/+1
2021-07-21	board: sifive: drop stuff related to unmatched revision 1	Zong Li	4	-1501/+1
2021-07-21	riscv: booti: do not force relocation if force_reloc is not set	Vitaly Wool	1	-1/+6
2021-07-07	riscv: dts: add OpenPiton RISC-V board dts support	Tianrui Wei	1	-2/+2
2021-07-06	riscv: dts: add dts for unmatched rev1	Zong Li	4	-1/+1501
2021-07-06	board: sifive: Add an interface to get PCB revision	Zong Li	1	-0/+15
2021-07-06	riscv: sifive: fu740: Support i2c in spl	Zong Li	2	-0/+5
2021-07-06	riscv: sifive: fu740: kconfig: Enable support for Opencores I2C controller	Zong Li	1	-0/+2
2021-07-06	board: riscv: add openpiton-riscv64 SoC support	Tianrui Wei	3	-0/+158
2021-06-28	Merge tag 'v2021.07-rc5' into next	Tom Rini	4	-8/+64
2021-06-17	k210: dts: Set PLL1 to the same rate as PLL0	Sean Anderson	1	-0/+2
2021-06-17	riscv: andes_plic: Fix riscv_get_ipi() mask	Bin Meng	1	-1/+3
2021-06-17	riscv: ae350: dts: Add missing "u-boot, dm-spl" for SPL config	Bin Meng	3	-0/+54
2021-06-17	riscv: ae350: dts: Fix #interrupt-cells for plic0 in 32-bit	Bin Meng	1	-1/+1
2021-06-17	riscv: ae350: dts: Remove the unnecessary #address-cells in plic nodes	Bin Meng	2	-4/+0
2021-06-17	riscv: ae350: dts: Remove the unnecessary space in bootargs	Bin Meng	2	-2/+2
2021-06-17	riscv: ae350: dts: Add SPDX license header	Bin Meng	2	-0/+4
2021-05-31	riscv: cpu: fu740: clear feature disable CSR	Green Wan	1	-0/+15
2021-05-31	board: sifive: add HiFive Unmatched board support	Green Wan	1	-0/+4
2021-05-31	riscv: dts: add SiFive Unmatched board support	Green Wan	4	-0/+1790
2021-05-31	riscv: dts: add fu740 support	Green Wan	2	-0/+434
2021-05-31	drivers: clk: add fu740 support	Green Wan	1	-1/+1
2021-05-31	riscv: cpu: fu740: Add support for cpu fu740	Green Wan	12	-0/+281
2021-05-24	treewide: Convert macro and uses of __section(foo) to __section("foo")	Marek Behún	1	-2/+2
2021-05-19	riscv: Drop USE_SPL_FIT_GENERATOR	Bin Meng	1	-100/+0
2021-05-19	riscv: ae350: Switch to use binman to generate u-boot.itb	Bin Meng	2	-0/+4
2021-05-19	riscv: qemu: Switch to use binman to generate u-boot.itb	Bin Meng	4	-0/+18
2021-05-19	riscv: dts: Sort build targets in alphabetical order	Bin Meng	1	-1/+1
2021-05-19	riscv: sifive: unleashed: Switch to use binman to generate u-boot.itb	Bin Meng	2	-0/+71
2021-05-17	riscv: Group assembly optimized implementation of memory routines into a submenu	Bin Meng	1	-0/+4
2021-05-17	riscv: Fix memmove and optimise memcpy when misalign	Bin Meng	2	-142/+257
2021-05-17	riscv: Fix arch_fixup_fdt always failing without /chosen	Sean Anderson	1	-4/+7
2021-05-17	riscv: Split SiFive CLINT support between SPL and U-Boot proper	Bin Meng	5	-5/+13
2021-05-14	Revert "riscv: cpu: fu740: clear feature disable CSR"	Bin Meng	1	-15/+0
2021-05-14	riscv: Don't reserve AI ram in k210 dts	Sean Anderson	1	-12/+0
2021-05-14	riscv: k210: Use AI as the parent clock of aisram, not PLL1	Sean Anderson	1	-1/+1
2021-05-14	riscv: k210: Rename airam to aisram	Sean Anderson	1	-2/+2
2021-05-14	riscv: Enable some devices pre-relocation	Sean Anderson	1	-0/+4
2021-05-05	riscv: cpu: fu740: clear feature disable CSR	Green Wan	1	-0/+15