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starfive-tech/u-boot.git
Fedora_JH7100_2021.04
Fedora_JH7100_2021.07
Fedora_JH7100_upstream
Fedora_JH7100_upstream_devel
JH7100_Multimedia_V0.1.0
JH7100_VisionFive_OH_dev
JH7100_VisionFive_devel
JH7100_starlight_multimedia
JH7100_upstream
JH7100_upstream_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_devel-v3.9.3
dubhe_fpga_dev_v2023.10
master
rtthread_AMP
visionfive_devel
StarFive Tech U-Boot for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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arch
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x86
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cpu
Age
Commit message (
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)
Author
Files
Lines
2015-01-13
x86: coreboot: Configure pci memory regions
Bin Meng
1
-2
/
+28
2015-01-13
x86: coreboot: Move coreboot-specific defines from coreboot.h to Kconfig
Bin Meng
1
-0
/
+15
2015-01-13
x86: coreboot: Set up timer base correctly
Bin Meng
1
-13
/
+20
2015-01-13
x86: fsp: Drop get_hob_type() and get_hob_length()
Bin Meng
2
-7
/
+7
2015-01-13
x86: ivybridge: Update microcode early in boot
Simon Glass
3
-10
/
+34
2015-01-13
x86: Disable CAR before relocation on platforms that need it
Simon Glass
1
-0
/
+8
2015-01-13
x86: ivybridge: Add a way to turn off the CAR
Simon Glass
1
-0
/
+46
2015-01-13
x86: ivybridge: Request MTRRs for DRAM regions
Simon Glass
1
-0
/
+10
2015-01-13
x86: ivybridge: Set up an MTRR for the video frame buffer
Simon Glass
1
-0
/
+7
2015-01-13
x86: Add support for MTRRs
Simon Glass
4
-18
/
+98
2015-01-13
x86: ivybridge: Drop support for ROM caching
Simon Glass
1
-25
/
+0
2015-01-13
x86: ivybridge: Only run the Video BIOS when video is enabled
Simon Glass
1
-1
/
+8
2015-01-13
x86: Simplify the fsp hob access functions
Bin Meng
2
-62
/
+72
2015-01-13
pci: Make pci apis usable before relocation
Bin Meng
1
-4
/
+4
2015-01-13
x86: Support pci bus scan in the early phase
Bin Meng
1
-0
/
+1
2015-01-13
x86: Add missing DECLARE_GLOBAL_DATA_PTR for pci.c
Bin Meng
1
-0
/
+2
2014-12-19
x86: Clean up the FSP support codes
Bin Meng
3
-144
/
+129
2014-12-19
x86: crownbay: Add SDHCI support
Bin Meng
2
-1
/
+48
2014-12-19
x86: crownbay: Add SPI flash support
Bin Meng
1
-1
/
+25
2014-12-19
x86: Use consistent name XXX_ADDR for binary blob flash address
Bin Meng
4
-5
/
+5
2014-12-19
x86: Add queensbay and crownbay Kconfig files
Bin Meng
1
-0
/
+79
2014-12-19
x86: Enable the queensbay cpu directory build
Bin Meng
1
-0
/
+1
2014-12-19
x86: Convert microcode format to device-tree-only
Simon Glass
1
-7
/
+4
2014-12-19
x86: Add basic support to queensbay platform and crownbay board
Bin Meng
5
-0
/
+323
2014-12-19
x86: Correct problems in the microcode loading
Simon Glass
1
-10
/
+15
2014-12-19
x86: ivybridge: Update the microcode
Simon Glass
1
-0
/
+2
2014-12-14
x86: Support Intel FSP initialization path in start.S
Bin Meng
1
-0
/
+14
2014-12-14
x86: Add post failure codes for bist and car
Bin Meng
1
-0
/
+1
2014-12-14
x86: queensbay: Adapt FSP support codes
Bin Meng
2
-17
/
+27
2014-12-14
x86: Initial import from Intel FSP release for Queensbay platform
Bin Meng
2
-0
/
+426
2014-12-14
x86: Clean up asm-offsets
Bin Meng
1
-1
/
+2
2014-12-08
Replace <compiler.h> with <linux/compiler.h>
Masahiro Yamada
1
-1
/
+2
2014-11-25
x86: Add initial video device init for Intel GMA
Simon Glass
4
-1
/
+925
2014-11-25
x86: Add GDT descriptors for option ROMs
Simon Glass
1
-3
/
+6
2014-11-25
x86: ivybridge: Add northbridge init functions
Simon Glass
3
-0
/
+191
2014-11-25
x86: Add init for model 206AX CPU
Simon Glass
3
-0
/
+521
2014-11-25
x86: Add LAPIC setup code
Simon Glass
2
-0
/
+58
2014-11-25
x86: Drop old CONFIG_INTEL_CORE_ARCH code
Simon Glass
1
-28
/
+0
2014-11-25
x86: Refactor interrupt_init()
Bin Meng
1
-6
/
+20
2014-11-25
x86: Remove cpu_init_r() for x86
Bin Meng
1
-6
/
+0
2014-11-25
x86: Call cpu_init_interrupts() from interrupt_init()
Bin Meng
1
-2
/
+0
2014-11-25
x86: Add Intel speedstep and turbo mode code
Simon Glass
2
-0
/
+99
2014-11-25
x86: ivybridge: Set up XHCI USB
Simon Glass
2
-0
/
+33
2014-11-25
x86: ivybridge: Set up EHCI USB
Simon Glass
3
-0
/
+32
2014-11-25
x86: ivybridge: Add SATA init
Simon Glass
3
-0
/
+246
2014-11-25
x86: ivybridge: Add additional LPC init
Simon Glass
2
-1
/
+528
2014-11-25
x86: ivybridge: Add PCH init
Simon Glass
2
-0
/
+124
2014-11-25
x86: ivybridge: Add support for BD82x6x PCH
Simon Glass
3
-0
/
+140
2014-11-25
x86: pci: Add handlers before and after a PCI hose scan
Simon Glass
1
-0
/
+12
2014-11-25
x86: Factor out common values in the link script
Simon Glass
2
-7
/
+12
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