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path: root/arch/x86/cpu
AgeCommit message (Expand)AuthorFilesLines
2015-01-13x86: coreboot: Configure pci memory regionsBin Meng1-2/+28
2015-01-13x86: coreboot: Move coreboot-specific defines from coreboot.h to KconfigBin Meng1-0/+15
2015-01-13x86: coreboot: Set up timer base correctlyBin Meng1-13/+20
2015-01-13x86: fsp: Drop get_hob_type() and get_hob_length()Bin Meng2-7/+7
2015-01-13x86: ivybridge: Update microcode early in bootSimon Glass3-10/+34
2015-01-13x86: Disable CAR before relocation on platforms that need itSimon Glass1-0/+8
2015-01-13x86: ivybridge: Add a way to turn off the CARSimon Glass1-0/+46
2015-01-13x86: ivybridge: Request MTRRs for DRAM regionsSimon Glass1-0/+10
2015-01-13x86: ivybridge: Set up an MTRR for the video frame bufferSimon Glass1-0/+7
2015-01-13x86: Add support for MTRRsSimon Glass4-18/+98
2015-01-13x86: ivybridge: Drop support for ROM cachingSimon Glass1-25/+0
2015-01-13x86: ivybridge: Only run the Video BIOS when video is enabledSimon Glass1-1/+8
2015-01-13x86: Simplify the fsp hob access functionsBin Meng2-62/+72
2015-01-13pci: Make pci apis usable before relocationBin Meng1-4/+4
2015-01-13x86: Support pci bus scan in the early phaseBin Meng1-0/+1
2015-01-13x86: Add missing DECLARE_GLOBAL_DATA_PTR for pci.cBin Meng1-0/+2
2014-12-19x86: Clean up the FSP support codesBin Meng3-144/+129
2014-12-19x86: crownbay: Add SDHCI supportBin Meng2-1/+48
2014-12-19x86: crownbay: Add SPI flash supportBin Meng1-1/+25
2014-12-19x86: Use consistent name XXX_ADDR for binary blob flash addressBin Meng4-5/+5
2014-12-19x86: Add queensbay and crownbay Kconfig filesBin Meng1-0/+79
2014-12-19x86: Enable the queensbay cpu directory buildBin Meng1-0/+1
2014-12-19x86: Convert microcode format to device-tree-onlySimon Glass1-7/+4
2014-12-19x86: Add basic support to queensbay platform and crownbay boardBin Meng5-0/+323
2014-12-19x86: Correct problems in the microcode loadingSimon Glass1-10/+15
2014-12-19x86: ivybridge: Update the microcodeSimon Glass1-0/+2
2014-12-14x86: Support Intel FSP initialization path in start.SBin Meng1-0/+14
2014-12-14x86: Add post failure codes for bist and carBin Meng1-0/+1
2014-12-14x86: queensbay: Adapt FSP support codesBin Meng2-17/+27
2014-12-14x86: Initial import from Intel FSP release for Queensbay platformBin Meng2-0/+426
2014-12-14x86: Clean up asm-offsetsBin Meng1-1/+2
2014-12-08Replace <compiler.h> with <linux/compiler.h>Masahiro Yamada1-1/+2
2014-11-25x86: Add initial video device init for Intel GMASimon Glass4-1/+925
2014-11-25x86: Add GDT descriptors for option ROMsSimon Glass1-3/+6
2014-11-25x86: ivybridge: Add northbridge init functionsSimon Glass3-0/+191
2014-11-25x86: Add init for model 206AX CPUSimon Glass3-0/+521
2014-11-25x86: Add LAPIC setup codeSimon Glass2-0/+58
2014-11-25x86: Drop old CONFIG_INTEL_CORE_ARCH codeSimon Glass1-28/+0
2014-11-25x86: Refactor interrupt_init()Bin Meng1-6/+20
2014-11-25x86: Remove cpu_init_r() for x86Bin Meng1-6/+0
2014-11-25x86: Call cpu_init_interrupts() from interrupt_init()Bin Meng1-2/+0
2014-11-25x86: Add Intel speedstep and turbo mode codeSimon Glass2-0/+99
2014-11-25x86: ivybridge: Set up XHCI USBSimon Glass2-0/+33
2014-11-25x86: ivybridge: Set up EHCI USBSimon Glass3-0/+32
2014-11-25x86: ivybridge: Add SATA initSimon Glass3-0/+246
2014-11-25x86: ivybridge: Add additional LPC initSimon Glass2-1/+528
2014-11-25x86: ivybridge: Add PCH initSimon Glass2-0/+124
2014-11-25x86: ivybridge: Add support for BD82x6x PCHSimon Glass3-0/+140
2014-11-25x86: pci: Add handlers before and after a PCI hose scanSimon Glass1-0/+12
2014-11-25x86: Factor out common values in the link scriptSimon Glass2-7/+12
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