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Fedora_JH7100_2021.04
Fedora_JH7100_2021.07
Fedora_JH7100_upstream
Fedora_JH7100_upstream_devel
JH7100_Multimedia_V0.1.0
JH7100_VisionFive_OH_dev
JH7100_VisionFive_devel
JH7100_starlight_multimedia
JH7100_upstream
JH7100_upstream_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_devel-v3.9.3
dubhe_fpga_dev_v2023.10
master
rtthread_AMP
visionfive_devel
StarFive Tech U-Boot for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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arch
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x86
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include
Age
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Author
Files
Lines
2015-01-13
x86: fsp: Drop get_hob_type() and get_hob_length()
Bin Meng
2
-34
/
+4
2015-01-13
x86: ivybridge: Update microcode early in boot
Simon Glass
1
-0
/
+6
2015-01-13
x86: Add support for MTRRs
Simon Glass
2
-83
/
+89
2015-01-13
x86: Drop RAMTOP Kconfig
Simon Glass
1
-8
/
+0
2015-01-13
x86: Simplify the fsp hob access functions
Bin Meng
2
-30
/
+21
2015-01-13
pci: Make pci apis usable before relocation
Bin Meng
2
-2
/
+1
2014-12-19
x86: Clean up the FSP support codes
Bin Meng
9
-134
/
+140
2014-12-19
x86: crownbay: Add SPI flash support
Bin Meng
1
-0
/
+15
2014-12-19
x86: ich6-gpio: Add Intel Tunnel Creek GPIO support
Bin Meng
2
-2
/
+15
2014-12-19
x86: Add basic support to queensbay platform and crownbay board
Bin Meng
1
-0
/
+3
2014-12-15
x86: move arch-specific asmlinkage to <asm/linkage.h>
Masahiro Yamada
3
-1
/
+8
2014-12-14
x86: Support Intel FSP initialization path in start.S
Bin Meng
1
-0
/
+3
2014-12-14
x86: Add post failure codes for bist and car
Bin Meng
1
-0
/
+2
2014-12-14
x86: queensbay: Adapt FSP support codes
Bin Meng
1
-1
/
+1
2014-12-14
x86: Initial import from Intel FSP release for Queensbay platform
Bin Meng
10
-0
/
+1096
2014-12-14
x86: Add a simple superio driver for SMSC LPC47M
Bin Meng
1
-0
/
+90
2014-12-14
x86: ich6-gpio: Move setup_pch_gpios() to board support codes
Bin Meng
3
-0
/
+7
2014-12-08
Replace <compiler.h> with <linux/compiler.h>
Masahiro Yamada
3
-3
/
+3
2014-11-25
x86: Add initial video device init for Intel GMA
Simon Glass
1
-0
/
+2
2014-11-25
x86: Add GDT descriptors for option ROMs
Simon Glass
1
-19
/
+12
2014-11-25
x86: ivybridge: Add northbridge init functions
Simon Glass
2
-1
/
+16
2014-11-25
x86: Drop some msr functions that we don't support
Simon Glass
1
-11
/
+0
2014-11-25
x86: Add init for model 206AX CPU
Simon Glass
2
-0
/
+5
2014-11-25
x86: Add LAPIC setup code
Simon Glass
2
-2
/
+123
2014-11-25
x86: Refactor interrupt_init()
Bin Meng
1
-0
/
+2
2014-11-25
x86: Remove cpu_init_r() for x86
Bin Meng
1
-2
/
+0
2014-11-25
x86: Add Intel speedstep and turbo mode code
Simon Glass
2
-0
/
+120
2014-11-25
x86: ivybridge: Set up XHCI USB
Simon Glass
1
-0
/
+1
2014-11-25
x86: ivybridge: Set up EHCI USB
Simon Glass
1
-0
/
+1
2014-11-25
x86: ivybridge: Add SATA init
Simon Glass
2
-0
/
+60
2014-11-25
x86: ivybridge: Add PCH init
Simon Glass
1
-0
/
+49
2014-11-25
x86: Add a simple header file for ACPI
Simon Glass
1
-0
/
+24
2014-11-25
x86: ivybridge: Add support for BD82x6x PCH
Simon Glass
2
-0
/
+27
2014-11-25
x86: Set up edge triggering on interrupt 9
Simon Glass
1
-0
/
+11
2014-11-25
x86: pci: Add handlers before and after a PCI hose scan
Simon Glass
1
-0
/
+3
2014-11-25
x86: Add ioapic.h header
Simon Glass
1
-0
/
+38
2014-11-21
x86: ivybridge: Implement SDRAM init
Simon Glass
8
-0
/
+613
2014-11-21
x86: ivybridge: Add LAPIC support
Simon Glass
2
-0
/
+160
2014-11-21
x86: ivybridge: Add support for early GPIO init
Simon Glass
4
-6
/
+158
2014-11-21
x86: ivybridge: Add early init for PCH devices
Simon Glass
4
-1
/
+237
2014-11-21
x86: ivybridge: Perform Intel microcode update on boot
Simon Glass
1
-0
/
+20
2014-11-21
x86: ivybridge: Perform initial CPU setup
Simon Glass
3
-0
/
+144
2014-11-21
x86: Add msr read/write functions that use a structure
Simon Glass
1
-0
/
+19
2014-11-21
x86: Add clr/setbits functions
Simon Glass
1
-0
/
+49
2014-11-21
x86: ivybridge: Add early LPC init so that serial works
Simon Glass
1
-0
/
+48
2014-11-21
x86: pci: Allow configuration before relocation
Simon Glass
1
-0
/
+13
2014-11-21
x86: Support use of PCI before relocation
Simon Glass
2
-0
/
+10
2014-11-21
x86: Refactor PCI to permit alternate init
Simon Glass
1
-0
/
+11
2014-11-21
x86: chromebook_link: Implement CAR support (cache as RAM)
Simon Glass
2
-1
/
+133
2014-11-21
x86: Emit post codes in startup code for Chromebooks
Simon Glass
1
-0
/
+32
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