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2020-05-19common: Drop bootstage.h from common headerSimon Glass4-0/+4
Move this fairly uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-19bootstage: Use BOOTSTAGE instead of BOOTSTATESimon Glass2-4/+4
Some of the enum members are wrong. Fix them. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-19common: Drop net.h from common headerSimon Glass1-0/+1
Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-17efi_loader: round the memory area in efi_add_memory_map()Michael Walle1-4/+2
Virtually all callers of this function do the rounding on their own. Some do it right, some don't. Instead of doing this in each caller, do the rounding in efi_add_memory_map(). Change the size parameter to bytes instead of pages and remove aligning and size calculation in all callers. There is no more need to make the original efi_add_memory_map() (which takes pages as size) available outside the module. Thus rename it to efi_add_memory_map_pg() and make it static to prevent further misuse outside the module. Signed-off-by: Michael Walle <michael@walle.cc> Add missing comma in sunxi_display.c. Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-05-04x86: Update SPL for corebootSimon Glass1-4/+6
At present SPL only works on bare-metal builds. With a few tweaks it can be used for coreboot also. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2020-05-04x86: Move work-around out of cpu_jump_to_64bit_uboot()Simon Glass1-0/+13
At present this function copies U-Boot from the last 1MB of ROM. This is not the right way to do it. Instead, the binman symbol should provide the location. But in any case the code should live in the caller, spl_board_load_image(), so that the 64-bit jump function can be used elsewhere. Move it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-30x86: cpu: Skip init code when chain loadingSimon Glass1-0/+3
When U-Boot is not the first-stage bootloader the interrupt and cache init must be skipped, as well as init for various peripherals. Update the code to add checks for this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-30x86: fsp: Allow skipping init code when chain loadingSimon Glass4-1/+22
It is useful to be able to boot the same x86 image on a device with or without a first-stage bootloader. For example, with chromebook_coral, it is helpful for testing to be able to boot the same U-Boot (complete with FSP) on bare metal and from coreboot. It allows checking of things like CPU speed, comparing registers, ACPI tables and the like. When U-Boot is not the first-stage bootloader much of this code is not needed and can break booting. Add checks for this to the FSP code. Rather than checking for the amount of available SDRAM, just use 1GB in this situation, which should be safe. Using 2GB may run into a memory hole on some SoCs. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-30acpi: Put table-setup code in its own functionSimon Glass1-76/+1
We always write three basic tables to ACPI at the start. Move this into its own function, along with acpi_fill_header(), so we can write a test for this code. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-04-30acpi: Move acpi_add_table() to generic codeSimon Glass1-73/+10
Move this code to a generic location so that we can test it with sandbox. This requires adding a few new fields to acpi_ctx, so drop the local variables used in the original code. Also use mapmem to avoid pointer-to-address casts which don't work on sandbox. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-04-30acpi: Drop code for missing XSDT from acpi_write_rsdp()Simon Glass1-13/+2
We don't actually support tables without an XSDT so we can drop this dead code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-04-30x86: Allow devices to write ACPI tablesSimon Glass1-0/+2
Call the new core function to permit devices to write their own ACPI tables. These tables will appear after all other tables. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-04-30acpi: Convert part of acpi_table to use acpi_ctxSimon Glass1-45/+43
The current code uses an address but a pointer would result in fewer casts. Also it repeats the alignment code in a lot of places so this would be better done in a helper function. Update write_acpi_tables() to make use of the new acpi_ctx structure, adding a few helpers to clean things up. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-04-30acpi: Add a method to write tables for a deviceSimon Glass1-9/+0
A device may want to write out ACPI tables to describe itself to Linux. Add a method to permit this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-04-16x86: Move acpi_table header to main include/ directorySimon Glass5-5/+5
This file is potentially useful to other architectures saddled with ACPI so move most of its contents to a common location. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-04-16x86: Move acpi_s3.h to include/acpi/Simon Glass5-5/+5
This header relates to ACPI and we are about to add some more ACPI headers. Move this one into a new directory so they are together. The header inclusion in pci_rom.c is not specific to x86 anymore, so drop the #ifdef CONFIG_X86. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-16x86: acpi: Let OS know that console already had been initializedAndy Shevchenko1-0/+9
SPCR has no clue if the UART base clock speed is different to the default one. However, the SPCR 1.04 defines baud rate 0 as a preconfigured state of UART and OS is supposed not to touch the configuration of the serial device. Linux kernel supports that starting from v5.0, see commit b413b1abeb21 ("ACPI: SPCR: Consider baud rate 0 as preconfigured state") for the details. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-04x86: acpi: Refactor XSDT handling in acpi_add_table()Andy Shevchenko1-18/+19
There is no need to have an assignment to NULL for XSDT pointer. Therefore, no need to assign it when rsdt_address is not set. Because of above changes we may decrease indentation level as well. While here, drop unnecessary parentheses. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-03-05x86: Correct error return value in mrccache_get_region()Simon Glass1-0/+2
This function doesn't use uclass_find_first_device() correctly. Add a check that the device is found so we don't try to read properties from a NULL device. The fixes booting on minnoxmax. Fixes: 87f1084a630 ("x86: Adjust mrccache_get_region() to use livetree") Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-06dm: core: Create a new header file for 'compat' featuresSimon Glass4-0/+4
At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-18common: Move hang() to the same header as panic()Simon Glass3-0/+3
At present panic() is in the vsprintf.h header file. That does not seem like an obvious choice for hang(), even though it relates to panic(). So let's put hang() in its own header. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Migrate a few more files] Signed-off-by: Tom Rini <trini@konsulko.com>
2019-12-15x86: Don't include the BIOS emulator in TPLSimon Glass1-0/+2
We don't generally have enough space to run this, so don't build it into TPL. This helps reduce the size of TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: fsp: Set up an MTRR for the graphics frame bufferSimon Glass1-0/+4
The FSP-S may do this but at least for coral it does not. Set this up so that graphics is not deathly slow. It isn't clear whether the FSP is expected to set up MTRR. It is not mentioned in the APL FSP document. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: fsp: Add FSP2 base supportSimon Glass7-0/+574
Add support for some important configuration options and FSP memory init. The memory init uses swizzle tables from the device tree. Support for the FSP_S binary is also included. Bootstage timing is used for both FSP_M and FSP_S and memory-mapped SPI reads. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: fsp: Correct wrong header inlude in fsp_support.cSimon Glass1-1/+1
This generic FSP file should include the generic FSP support header, not the FSP1 version. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: fsp: Make graphics support common to FSP1/2Simon Glass3-2/+4
Both versions of FSP can use the same graphics support, so move it into the common directory. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: Allow interrupt to happen onceSimon Glass1-0/+10
At present the interrupt table is included in all phases of U-Boot. Allow it to be omitted, e.g. in TPL, to reduce size. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: Set up the MTRR for SDRAMSimon Glass1-0/+5
Set up MTRRs for the FSP SDRAM regions to improve performance. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: Set the DRAM banks to reflect real locationSimon Glass1-1/+29
At present with fsp a single DRAM bank is added which extends to the whole size of memory. However there is typically only 2GB of memory available below the 4GB boundary, and this is what is used by U-Boot while running in 32-bit mode. Scan the tables to set the banks correct. The first bank is set to memory below 4GB, and the rest of memory is put into subsequent banks. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: Move fsp_prepare_mrc_cache() to fsp1 directorySimon Glass2-20/+20
This function needs to be different for FSP2, so move the existing function into the fsp1 directory. Since it is only called from one file, drop it from the header file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: Don't export mrccache_update()Simon Glass1-2/+14
This function is only used within the implementation so make it static. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: Add mrccache support for a 'variable' cacheSimon Glass1-1/+2
Add support for a second cache type, for Apollo Lake. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: Update mrccache to support multiple cachesSimon Glass3-34/+64
With Apollo Lake we need to support a normal cache, which almost never changes and a much smaller 'variable' cache which changes every time. Update the code to add a cache type, use an array for the caches and use a for loop to iterate over the caches. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: Tidy up error handling in mrccache_save()Simon Glass1-12/+7
This function is a bit confusing at present due to the error handling. Update it to remove the goto, returning errors as they happen. While we are here, use hex for the data size since this is the norm in U-Boot. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: Add a new global_data member for the cache recordSimon Glass1-6/+5
At present we reuse the mrc_output char * to also point to the cache record after it has been set up. This is confusing and doesn't save much data space. Add a new mrc_cache member instead. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: Adjust mrccache_get_region() to support get_mmap()Simon Glass1-4/+14
It is now possible to obtain the memory map for a SPI controllers instead of having it hard-coded in the device tree. Update the code to support this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: Adjust mrccache_get_region() to use livetreeSimon Glass1-29/+26
Change the algorithm to first find the flash device then read the properties using the livetree API. With this change the device is not probed so this needs to be done in mrccache_save(). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15x86: Correct mrccache find_next_mrc_cache() calculationSimon Glass1-4/+14
This should take account of the end of the new cache record since a record cannot extend beyond the end of the flash region. This problem was not seen before due to the alignment of the relatively small amount of MRC data. But with Apollo Lake the MRC data is about 45KB, even if most of it is zeroes. Fix this bug and update the parameter name to be less confusing. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-03common: Move board_get_usable_ram_top() out of common.hSimon Glass2-0/+2
Move this function into init.h which seems to be designed for this sort of thing. Also update the header to declare struct global_data so that it can be included without global_data.h being needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-03common: Move enable/disable_interrupts out of common.hSimon Glass1-0/+1
Move these two functions into the irq_funcs.h header file. Also move interrupt_handler_t as this is used by the irq_install_handler() function. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-03common: Move interrupt functions into a new headerSimon Glass3-0/+3
These functions do not use driver model but are fairly widely used in U-Boot. But it is not clear that they will use driver model anytime soon, so we don't want to label them as 'legacy'. Move them to a new irq_func.h header file. Avoid the name 'irq.h' since it is widely used in U-Boot already. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-03common: Move some cache and MMU functions out of common.hSimon Glass1-0/+1
These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-03common: Move checkcpu() out of common.hSimon Glass1-0/+1
This function belongs in cpu_func.h so move it over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-11-03x86: Quieten TPL's jump_to_image_no_args()Simon Glass1-1/+1
We already a message indicating that U-Boot is about to jump to SPL, so make this one a debug() to reduce code size. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-11-03x86: Don't print CPU info in TPLSimon Glass1-5/+0
We don't need to do this and it is done (in more detail) in U-Boot proper. Drop this to save code space. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-11-03x86: Move CPU init to before spl_init()Simon Glass2-0/+9
At present we call spl_init() before identifying the CPU. This is not a good idea - e.g. if bootstage is enabled then it will try to set up the timer which works better if the CPU is identified. Put explicit code at each entry pointer to identify the CPU. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-11-03x86: tpl: Add a fake PCI busSimon Glass1-0/+25
In TPL we try to minimise code size so do not include the PCI subsystem. We can use fixed BARs and drivers can directly program the devices that they need. However we do need to bind the devices on the PCI bus and without PCI this does not ordinarily happen. As a work-around, define a fake PCI bus which does this binding, but no other PCI operations. This is a convenient way to ensure that we can use the same device tree for TPL, SPL and U-Boot proper: TPL - CONFIG_TPL_PCI is not set (no auto-config, fake PCI bus) SPL - CONFIG_SPL_PCI is set (no auto-config but with real PCI bus) U-Boot - CONFIG_PCI is set (full auto-config after relocation) Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-11-03x86: spl: Support init of a PUNITSimon Glass1-0/+40
The x86 power unit handles power management. Support initing this device which is modelled as a new type of system controller since there are no operations needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-11x86: Add a function to find the size of an mrccache recordSimon Glass1-7/+8
Move the code to determine the size of a cache record into a function so we can use it elsewhere in this file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-11x86: Panic when SPL or TPL failSimon Glass2-2/+2
At present when these fail to boot there is no message, just a hang. Add a panic so it is obvious that something when wrong. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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