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2021-11-07efi: Add video support to the appSimon Glass1-0/+4
The current EFI video driver only works when running in the stub. In that case the stub calls boot services (before jumping to U-Boot proper) and copies the graphics info over to the efi table. This is necessary because the stub exits boot services before jumping to U-Boot. The app maintains access to boot services throughout its life, so does not need to do this. Update the driver to support calling boot services directly. Enable video output for the app. Note that this uses the EFI_GRAPHICS_OUTPUT_PROTOCOL protocol, even though it mentions vesa. A sample qemu command-line for this case is: qemu-system-x86_64 -bios /usr/share/edk2.git/ovmf-ia32/OVMF-pure-efi.fd -drive id=disk,file=try.img,if=none,format=raw -nic none -device ahci,id=ahci -device ide-hd,drive=disk,bus=ahci.0 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-11-07x86: Don't duplicate global_ptr in 64-bit EFI appSimon Glass2-14/+17
This variable is already defined by the EFI code. Drop the duplicate definition when building a 64-bit EFI app. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-11-07efi: Create a 64-bit appSimon Glass4-17/+31
Most modern platforms use 64-bit EFI so it is useful to have a U-Boot app that runs under that. Add a (non-functional) build for this. Note that --whole-archive causes the gcc 9.2 linker to crash, so disable this for now. Once this is resolved, things should work. For now, avoid mentioning the documentation for the 64-bit app, since it does not work. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-11-07x86: Create a 32/64-bit selection for the appSimon Glass1-1/+1
Most EFI implementations use 64-bit but U-Boot only supports running as a 32-bit app at present. While efi-x86_payload64 does boot from 64-bit UEFI it immediately changes back to 32-bit before starting U-Boot. In order to support a 64-bit U-Boot app, update the Kconfig to add an option for 32/64 bit. Update the prompt for the existing option so it is clear it relates to the stub. Move both up to just under the choice that controls them, since this looks better and the menu. Use CONFIG_EFI_APP in the Makefile instead of CONFIG_TARGET_EFI_APP, since the latter is specific to a single target and we will have two. Memory size is set to 32MB for now so that it can run on qemu without increasing the default memory size. We may need to increase the default later. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-11-01x86: tangier: pinmux: Move error message to the callerAndy Shevchenko1-7/+3
Move error message to the caller of mrfld_pinconfig*() in order to unify them in the future. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-11-01x86: tangier: pinmux: Move is_protected assignment closer to its userAndy Shevchenko1-2/+1
Move is_protected assignment closer to its user. This increases readability and makes maintenance easier. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-11-01x86: edison: Don't take SD card detect pin into considerationAndy Shevchenko1-0/+17
There are two PCB designs in the wild which use the opposite signaling for SD card detection. This makes U-Boot working in one case and failing in the other. Quirk this out by disconnecting SD card detection pin from the PCB by switching it to mode 3. In the disconnected state the read value is always the same and inverted to what we are expecting in the code. BugLink: https://github.com/edison-fw/meta-intel-edison/issues/136 Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-11-01x86: tangier: Enable support for SD/SDIO family in the pinmux driverAndy Shevchenko1-5/+34
We would need to quirk out the Card Detect case and for that we allow configuring the SD/SDIO family of pins. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-11-01x86: Fix i8254 ifdef include guardAlistair Delva1-2/+2
When building U-Boot with clang, it notices that the i8254.h include guard does not work correctly due to a typo. Fix it. Signed-off-by: Alistair Delva <adelva@google.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: fixed the other same typo at the end of the same file] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2021-11-01x86: chromebook_coral: fix C block commentAlistair Delva1-0/+1
Fix a warning seen when compiling this dts file. Signed-off-by: Alistair Delva <adelva@google.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-11-01x86: tangier: Replace Method() by Name() for _STA objectAndy Shevchenko1-64/+17
There is no point to use Method() for the constant. Replace it with Name() defined object. For the _STA case it saves 3 bytes per each entry. Before: 2881 After: 2833 Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-10-31bootstage: Add SPL supportMarek Vasut1-1/+1
Allow usage of the bootstage facilities in SPL. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-10-21x86: Show some EFI info with the bdinfo commandSimon Glass4-2/+41
It is useful to see some basic EFI info with the command as it forms part of the information about a board. Add a hook for this and show the table address as a start. While here, fix an invalid cast in setup_efi_info(). Note that this function is using a data structure defined by Linux so we cannot change it. Also note that ulong is used since this is the standard in U-Boot (>6k uses), despite there being quite a bit of the more verbose uintptr_t (930 uses). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-10-21x86: Create a new header for EFISimon Glass3-3/+33
The setup routines are called from zimage but don't really belong in the zimage header. Add a new EFI header to house these. Add comments so it is clear what the functions do. Note that these functions are x86-specific. The zimage business is not used on other architectures. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-10-21x86: Keep symbol information in u-boot ELF fileSimon Glass1-2/+2
At present this information is stripped when linking. It is useful to keep it around. Strip it from the .efi files instead. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-09-30WS cleanup: remove SPACE(s) followed by TABWolfgang Denk2-3/+3
Signed-off-by: Wolfgang Denk <wd@denx.de>
2021-09-27Merge tag 'dm-pull-next-27sep21' of ↵Tom Rini10-25/+24
https://source.denx.de/u-boot/custodians/u-boot-dm into next Various of-platdata improvements, including CONFIG_OF_REAL
2021-09-27Merge tag 'v2021.10-rc5' into nextTom Rini2-0/+33
Prepare v2021.10-rc5
2021-09-25treewide: Try to avoid the preprocessor with OF_REALSimon Glass1-10/+10
Convert some of these occurences to C code, where it is easy to do. This should help encourage this approach to be used in new code. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-25treewide: Use OF_REAL instead of !OF_PLATDATASimon Glass8-12/+12
Now that we have a 'positive' Kconfig option, use this instead of the negative one, which is harder to understand. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-25treewide: Simply conditions with the new OF_REALSimon Glass1-1/+1
Use this new Kconfig to simplify the compilation conditions where appropriate. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-25treewide: fdt: Move fdt_get_config_... to ofnode_conf_read...Simon Glass1-3/+2
The current API is outdated as it requires a devicetree pointer. Move these functions to use the ofnode API and update this globally. Add some tests while we are here. Correct the call in exynos_dsim_config_parse_dt() which is obviously wrong. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-23lmb: x86: Add arch_lmb_reserve()Marek Vasut1-0/+18
Add arch_lmb_reserve() implemented using arch_lmb_reserve_generic(). It is rather likely this architecture also needs to cover U-Boot with LMB before booting Linux. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Simon Glass <sjg@chromium.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tom Rini <trini@konsulko.com>
2021-09-22x86: tangier: acpi: Add GPIO card detection to SDHCI #2Andy Shevchenko1-0/+32
On Intel Tangier the SDHCI #2 provides SD card connection. Add GPIO card detection for it. Fixes: 39665beed6f7 ("x86: tangier: Enable ACPI support for Intel Tangier") BugLink: https://github.com/edison-fw/meta-intel-edison/issues/135 Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Bin Meng <bmeng.cn@gmail.com>
2021-09-22x86: edison: Mark eMMC non-removableAndy Shevchenko1-0/+1
eMMC is non-removable on Intel Edison board. Fix the DTS accordingly. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-09-17x86: quark: MRC: Remove U_BOOT_DATE and U_BOOT_TIME from debug logPali Rohár1-3/+1
U_BOOT_DATE and U_BOOT_TIME are updated on every run of make command. Therefore mrc.c file is recompiled every time when running make which means that whole U-Boot binary is recompiled on every run of make command. Simplify it and do not recompile U-Boot binary on every run of make command by not depending on macros U_BOOT_DATE and U_BOOT_TIME. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-09-17Remove #include <version.h> from files which do not need itPali Rohár1-1/+0
Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2021-09-04spi: Rename SPI_SUPPORT to SPISimon Glass1-1/+1
Rename these options so that CONFIG_IS_ENABLED can be used with them. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-04pch: Rename PCH_SUPPORT to PCHSimon Glass1-3/+3
Rename these options so that CONFIG_IS_ENABLED can be used with them. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-01Kconfig: Remove all default n/no optionsMichal Simek2-13/+1
default n/no doesn't need to be specified. It is default option anyway. Signed-off-by: Michal Simek <michal.simek@xilinx.com> [trini: Rework FSP_USE_UPD portion] Signed-off-by: Tom Rini <trini@konsulko.com>
2021-09-01Finish converting CONFIG_SYS_CACHELINE_SIZE to KconfigTom Rini1-6/+1
We move the SYS_CACHE_SHIFT_N options from arch/arm/Kconfig to arch/Kconfig, and introduce SYS_CACHE_SHIFT_4 to provide a size of 16. Introduce select statements for other architectures based on current usage. For MIPS, we take the existing arch-specific symbol and migrate to the generic symbol. This lets us remove a little bit of otherwise unused code. Cc: Alexey Brodkin <alexey.brodkin@synopsys.com> Cc: Anup Patel <anup.patel@wdc.com> Cc: Atish Patra <atish.patra@wdc.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Leo <ycliang@andestech.com> Cc: Palmer Dabbelt <palmer@dabbelt.com> Cc: Paul Walmsley <paul.walmsley@sifive.com> Cc: Sean Anderson <seanga2@gmail.com> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
2021-08-17efi_loader rename enum efi_mem_type to efi_memory_typeHeinrich Schuchardt1-1/+1
Use the same name as in the UEFI specification to avoid confusion. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2021-08-03Merge https://source.denx.de/u-boot/custodians/u-boot-x86Tom Rini30-89/+101
- Fixed broken ICH SPI driver in software sequencer mode - Added "m25p,fast-read" to SPI flash node for x86 boards - Drop ROM_NEEDS_BLOBS and BUILD_ROM for x86 ROM builds - Define a default TSC timer frequency for all x86 boards - x86 MTRR MSR programming codes bug fixes - x86 "hob" command bug fixes - Don't program MTRR for DRAM for FSP1 - Move INIT_PHASE_END_FIRMWARE to FSP2 - Use external graphics card by default on Intel Crown Bay - tangier: Fix DMA controller IRQ polarity in CSRT
2021-08-02global: Convert simple_strtoul() with hex to hextoul()Simon Glass1-7/+7
It is a pain to have to specify the value 16 in each call. Add a new hextoul() function and update the code to use it. Add a proper comment to simple_strtoul() while we are here. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-08-02x86: queensbay: Return directly if IGD / SDVO were already disabledBin Meng1-11/+9
Initialize 'igd' and 'sdvo' to NULL so that we just need to test them against NULL later, to be compatible with that case that IGD and SDVO devices were already in disabled state. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-08-02x86: fsp: Only FSP2 has INIT_PHASE_END_FIRMWAREBin Meng2-16/+17
For FSP1, there is no such INIT_PHASE_END_FIRMWARE. Move board_final_cleanup() to fsp2 directory. Fixes: 7c73cea44290 ("x86: Notify the FSP of the 'end firmware' event") Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested on chromebook_coral, chromebook_samus, chromebook_link, minnowmax Tested-by: Simon Glass <sjg@chromium.org>
2021-08-02x86: fsp: Don't program MTRR for DRAM for FSP1Bin Meng1-4/+23
There are several outstanding issues as to why this does not apply to FSP1: * For FSP1, the system memory and reserved memory used by FSP are already programmed in the MTRR by FSP. * The 'mtrr_top' mistakenly includes TSEG memory range that has the same RES_MEM_RESERVED resource type. Its address is programmed and reported by FSP to be near the top of 4 GiB space, which is not what we want for SDRAM. * The call to mtrr_add_request() is not guaranteed to have its size to be exactly the power of 2. This causes reserved bits of the IA32_MTRR_PHYSMASK register to be written which generates #GP. For FSP2, it seems this is necessary as without this, U-Boot boot process on Chromebook Coral goes very slowly. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested on chromebook_coral, chromebook_samus, chromebook_link, minnowmax Tested-by: Simon Glass <sjg@chromium.org>
2021-08-02x86: mtrr: Abort if requested size is not power of 2Bin Meng2-3/+11
The size parameter of mtrr_add_request() and mtrr_set_next_var() shall be power of 2, otherwise the logic creates a mask that does not meet the requirement of IA32_MTRR_PHYSMASK register. Programming such a mask value to IA32_MTRR_PHYSMASK generates #GP. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested on chromebook_coral, chromebook_samus, chromebook_link, minnowmax Tested-by: Simon Glass <sjg@chromium.org>
2021-08-02x86: mtrr: Skip MSRs that were already programmed in mtrr_commit()Bin Meng1-1/+1
At present mtrr_commit() programs the MTRR MSRs starting from index 0, which may overwrite MSRs that were already programmed by previous boot stage or FSP. Switch to call mtrr_set_next_var() instead. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested on chromebook_coral, chromebook_samus, chromebook_link, minnowmax Tested-by: Simon Glass <sjg@chromium.org>
2021-08-02x86: mtrr: Do not clear the unused ones in mtrr_commit()Bin Meng1-4/+0
Current mtrr_commit() logic assumes that MTRR MSRs are programmed consecutively from index 0 to its maximum number, and whenever it detects an unused one, it clears all other MTRRs starting from that one. However this may not always be the case. In fact, the clear is not much helpful because these MTRRs come out of reset as disabled already. Drop the clear codes. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested on chromebook_coral, chromebook_samus, chromebook_link, minnowmax Tested-by: Simon Glass <sjg@chromium.org>
2021-08-02x86: dts: Define a default TSC timer frequencyBin Meng20-43/+25
If for some reason, TSC timer frequency cannot be determined from hardware, nor is it specified in the device tree, U-Boot will panic resulting in endless reset during boot. Let's define a default TSC timer frequency using the Kconfig value CONFIG_X86_TSC_TIMER_FREQ (note: #include must be used instead of /include/ otherwise the macro is not pre-processed). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-08-02x86: tsc: Rename X86_TSC_TIMER_EARLY_FREQ to X86_TSC_TIMER_FREQBin Meng2-3/+3
Currently there are two places to specify the x86 TSC timer frequency with one in Kconfig used for early timer and the other one in device tree used when the frequency cannot be determined from hardware. This may potentially create an inconsistent config where the 2 values do not match. Let's use the one specified in Kconfig in the device tree as well. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-08-02x86: kconfig: Drop ROM_NEEDS_BLOBS and BUILD_ROMBin Meng2-3/+0
These 2 options are no longer needed as now binman is used to build u-boot.rom. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-08-02x86: tangier: Fix DMA controller IRQ polarity in CSRTAndy Shevchenko1-2/+2
IRQ polarity in CSRT has the same definition as by ACPI specification chapter 19.6.64 "Interrupt (Interrupt Resource Descriptor Macro)", i.e. ActiveHigh is 0, and ActiveLow is 1. On Intel Tangier the DMA controller IRQ polarity is ActiveHigh. Note, in DSDT (see southcluster.asl) it's described correctly. Fixes: 5e99fde34a77 ("x86: tangier: Populate CSRT for shared DMA controller") Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-08-02x86: dts: Add "m25p,fast-read" to SPI flash nodeBin Meng11-0/+11
Except ICH7 SPI, all SPI flashes connected to ICH9 / Fast SPI should have "m25p,fast-read" property present in their DT nodes. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-07-24smbios: error handling for invalid addressesHeinrich Schuchardt1-2/+11
SMBIOS tables only support 32bit addresses. If we don't have memory here handle the error gracefully: * on x86_64 fail to start U-Boot * during UEFI booting ignore the missing table Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-07-15x86: Ensure the e820 map is installed in all casesSimon Glass1-4/+4
This is a revert of a recent logic change in setup_zimage(). We do actually need to install this information always. Change it to install from the Coreboot tables if available, else the normal source. Fixes: e7bae8283fe ("x86: Allow installing an e820 when booting from coreboot") Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-07-15x86: cros: Check ROM exists before building vbootSimon Glass2-2/+2
All the x86 devicetree files are built at once, whichever board is actually being built. If coreboot is the target build, CONFIG_ROM_SIZE is not defined and samus cannot build Chromium OS verified boot. Add this condition to avoid errors about CONFIG_ROM_SIZE being missing. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-07-15x86: coreboot: Use vendor in the KconfigSimon Glass1-1/+1
Use VENDOR_COREBOOT instead of TARGET_COREBOOT so we can have multiple coreboot boards, sharing options. Only SYS_CONFIG_NAME needs to be defined TARGET_COREBOOT. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-07-15x86: Add function comments to cb_sysinfo.hSimon Glass1-0/+16
Add a function comment for get_coreboot_info() and a declaration for cb_get_sysinfo(), since this may be called from elsewhere. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
generated by cgit v1.2.3 (git 2.39.0) at 2024-09-05 22:36:09 +0300