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Change Model to "StarFive JH7110 EVB", and change riscv,isa to
"rv64imafdcbsux"
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
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Add SPL_DM_RESET to defconfig, and update uart3-uart5 reset for StarFive
JH7110 SoC.
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
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Modify the default division factor of sdcard clk to 4.
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
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Add usb init config for starfive EVB board. Default set to USB2.0
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
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Remove pll0/pll1/pll2 clk define from jh7110_clk.dts to clk-jh7110.c
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
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High-speed emmc/sdio support
Signed-off-by: samin <samin.guo@starfivetech.com>
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Modify the GPIO configuration for sd&emmc module, switch the clk of sd&emmc
to high frequency
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
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Modify SD&EMMC node configuration on Starfive EVB board.
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
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Adjust CPU working frequency from 1G to 1.25G for starfive EVB board.
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
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Add ethernet-phy delay_chain configuration for gmac1 on starfive EVB
board.
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
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Clear L2 LIM memory on StarFive JH7110, avoid some unexpect exception.
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Add ddr device node for JH7110.
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
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Add clk init for ddr on JH7110 board
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
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Add JH7110_GMAC0_GTXC clk register and remove pll0/pll1/pll2 clk define
from clk-jh7110.c to jh7110_clk.dts
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
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Add macro definition of GPIO
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
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Add board support for StarFive EVB.
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
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Synchronize the kernel dts file
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
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Synchronize the kernel dts file
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
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The rtc timer is used early in kernel, but the clk&reset driver is not
ready,so some clk&reset init is placed here.
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
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Add board support for StarFive VisionFive.
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
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Add dts support for jh7110. The starfive visionfive support is based on
jh7110 soc.
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
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Add StarFive JH7110 soc to support RISC-V arch
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
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Support for GPIO controller on starfive JH7110 SoCs.
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
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https://source.denx.de/u-boot/custodians/u-boot-raspberrypi
- fix usb stopt; usb start; bug
- update Nicolas email address
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XHCI firmware upload must be performed only once after initializing the
PCI bridge. This fixes USB stack initialization after calling "usb stop;
usb start" on Raspberry Pi 4B.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Nicolas Saenz Julienne <nsaenz@kernel.org>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
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During the migration to a single DTSI for the CP110-s specific pinctrl
compatibles were moved to the SoC DTSI as CP0 and CP1 have some specifics.
Namely, CP0 eMMC/SDIO support depends on the mvebu-pinctrl driver setting
the BIT(0) in eMMC PHY IO Control 0 Register to 0 in order for the connect
the eMMC/SDIO PHY to the controller and not use it as a MPP pin multiplexor.
So, the mvebu-pinctrl driver check specifically for the
"marvell,armada-8k-cpm-pinctrl" compatible to clear the that bit.
Issue is that compatibles in the 8040 DTSI were set to "marvell,8k-cpm-pinctrl"
for CP0 and "marvell,8k-cps-pinctrl" for the CP1.
This is obviously incorrect as the pinctrl driver does not know about these.
So fix the regression by applying correct compatibles to the DTSI.
Regression found and tested on the Puzzle M801 board.
Fixes: a0ba97e5 ("arm: armada: dts: Use a single dtsi for cp110 die description")
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Reviewed-by: Stefan Roese <sr@denx.de>
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Commit 0d52bab46 (mx7dsabre: Enable DM_ETH) changed these flags from 0
(aka GPIO_ACTIVE_HIGH) to GPIO_ACTIVE_LOW. It claimed to "Also sync
device tree with v5.5-rc1", but in the linux tree, these gpios have
always been GPIO_ACTIVE_HIGH ever since this node was introduced
around v4.13 (linux commit 184f39b5).
I'm guessing that the reason for the GPIO_ACTIVE_LOW was to work
around the behaviour of the soft-spi driver back then, which
effectively defaulted to spi-mode 3 and not 0. That was arguably a bug
in the soft-spi driver, which then got fixed in 0e146993bb3 (spi: add
support for all spi modes with soft spi), but that commit then broke
ethernet on this board.
Fix it by setting the gpios as active high, which as a bonus actually
brings us in sync with the .dts in the linux source tree.
Without this, one gets
Net: Could not get PHY for FEC0: addr 0
No ethernet found.
With this, ethernet (at least ping and tftp) works as expected from
the U-Boot shell.
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Joris Offouga <offougajoris@gmail.com>
Cc: "Christian Bräuner Sørensen" <yocto@bsorensen.net>
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
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The USB peripheral controller is the DWC2 controller 1, not 0.
Update the phandle to fix UDC support on this board.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
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The WDT on this system should be enabled, make it so.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
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On Intel Tangier the SDHCI #2 provides SD card connection.
Add GPIO card detection for it.
Fixes: 39665beed6f7 ("x86: tangier: Enable ACPI support for Intel Tangier")
BugLink: https://github.com/edison-fw/meta-intel-edison/issues/135
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
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eMMC is non-removable on Intel Edison board. Fix the DTS accordingly.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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Continue to use the "ssbl" name for GPT partition of secondary boot
stage = U-Boot for basic boot with SPL to avoid to disturb existing user.
The "fip" partition name is only used for TFA_BOOT with FIP, it is a TF-A
BL2 requirement; it the default configuration for STMicroelectronics
boards.
Fixes: b73e8bf453f8 ("arm: stm32mp: add defconfig for trusted boot with FIP")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
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startup
With Device Manager firmware in an elf file form, we cannot load the FIT
image to the exact same address as any of the executable sections of the
elf file itself is located.
However, the device tree descriptions for the ARMV8 bootloader/OS
includes DDR regions only the final sections in DDR where the Device
Manager firmware is actually executing out of.
As the R5 uC is usually operating at a slower rate than an ARMv8 MPU,
by starting the Armv8 ahead of parsing the elf and copying the correct
sections to the required memories creates a race condition where the
ARMv8 could overwrite the elf image loaded from the FIT image prior to
the R5 completing parsing and putting the correct sections of elf in
the required memory locations. OR create rather obscure debug conditions
where data in the section is being modified by ARMV8 OS while the elf
copy is in progress.
To prevent all these conditions, lets make sure that the elf parse and
copy operations are completed ahead of ARMv8 being released to execute.
We will pay a penalty of elf copy time, but that is a valid tradeoff in
comparison to debug of alternate scenarios.
Signed-off-by: Nishanth Menon <nm@ti.com>
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NB0 is bridge to SRAM and NB1 is bridge to DDR.
To ensure that SRAM transfers are not stalled due to delays during DDR
refreshes, SRAM traffic should be higher priority (threadmap=2) than
DDR traffic (threadmap=0).
This fixup is critical to provide deterministic access latency to
MSMC from ICSSG, it applies to all AM65 silicon revisions and is due
to incorrect reset values (has no erratum id) and statically setting
things up should be done independent of usecases and board.
This specific style of Northbridge configuration is specific only to
AM65x devices, follow-on K3 devices have different data prioritization
schemes (ASEL and the like) and hence the fixup applies purely to
AM65x.
Without this fix, ICSSG TX lock-ups due to delays in MSMC transfers in
case of SR1 devices, on SR2 devices, lockups were not observed so far
but high retry rates of ICSSG Ethernet (icssg-eth) and, thus, lower
throughput.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Acked-by: Andrew F. Davis <afd@ti.com>
Acked-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: Benoit Parrot <bparrot@ti.com>
[Jan: rebased, dropped used define, extended commit log]
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
[Nishanth: Provide relevant context in the commit message]
Signed-off-by: Nishanth Menon<nm@ti.com>
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The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in
turn serve as inputs to other HSDIV output clocks. These clocks use
the actual value to compute the divider clock rate, and need to be
registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk
driver and data lacks the infrastructure to pass in divider flags.
Update the driver and data to account for these divider flags.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
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Add a note to the automatically generated clk-data and dev-data files
for j721e and j7200 to indicate that they are in fact auto-generated and
should not be hand edited.
Also adjust TI URL to use https instead of http and also add an empty
line before first header inclusion.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
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The TI K3 Fractional PLLs use two programmable POSTDIV1 and POSTDIV2
divisors to generate the final FOUTPOSTDIV clock. These are in sequence
with POSTDIV2 following the POSTDIV1 clock. The current J7200 clock data
has the POSTDIV2 clock as the parent for the POSTDIV1 clock, which is
opposite of the actual implementation. Fix the data by simply adjusting
the register bit-shifts.
The Main PLL1 POSTDIV clocks were also defined incorrectly using Main PLL0
register values, fix these as well.
Fixes: 277729eaf373 ("arm: mach-k3: Add platform data for j721e and j7200")
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
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The TI K3 Fractional PLLs use two programmable POSTDIV1 and POSTDIV2
divisors to generate the final FOUTPOSTDIV clock. These are in sequence
with POSTDIV2 following the POSTDIV1 clock. The current J721E clock data
has the POSTDIV2 clock as the parent for the POSTDIV1 clock, which is
opposite of the actual implementation. Fix the data by simply adjusting
the register bit-shifts.
The Main PLL1 POSTDIV clocks were also defined incorrectly using Main PLL0
register values, fix these as well.
Fixes: 277729eaf373 ("arm: mach-k3: Add platform data for j721e and j7200")
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
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Add a weak release_resources_for_core_shutdown() stub implementation
that can be overridden by actual implementation if a SoC supports that
function.
Signed-off-by: Suman Anna <s-anna@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
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Move the XHCI PCI device base up in the virtual address space. This fixes
initialization failure observed with newer Raspberry Pi firmware, later
than 63b1922311 ("firmware: arm_loader: Update armstubs with those from
PR 117). It looks that chosing 0xff800000 as the XHCI PCI device base
conflicts with the updated ARM/VideoCore firmware.
This also requires to reduce the size of the mapped PCI device region
from 8MiB to 4MiB to fit into 32bit address space. This is still enough
for the XHCI PCI device.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Nicolas Saenz Julienne <nsaenz@kernel.org>
Tested-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
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At present SMBIOS tables are empty, which breaks some use-cases that
rely on that. Add some minimal information to fulfill this.
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
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This option has not effect now. Drop it, using PCI instead where needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
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This board has not been converted to CONFIG_DM_PCI by the deadline.
Remove it.
Note that we have to add CONFIG_SPIFLASH to scripts/config_whitelist.txt
because it's not really migrated at this point.
Acked-by: Michael Durrant <mdurrant@arcturusnetworks.com>
Acked-by: Oleksandr Zhadan <oleks@arcturusnetworks.com>
Acked-by: Oleksandr Zhadan and Michael Durrant <arcsupport@arcturusnetworks.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Handle CONFIG_SPIFLASH differently and delete Kconfig file]
Signed-off-by: Tom Rini <trini@konsulko.com>
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In the cdns3 usb driver, the clock name looked for is ref. Therefore, fix
the clock-names property in usb0 instance for proper initialization of
cdns3 usb gadget driver.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
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As per Device Tree Specification [1], the status parameter of nodes can
be "okay", "disabled", etc. "ok" is not a valid parameter.
U-boot Driver Model does not recognize status="ok" either and treats
the node as disabled.
[1] https://github.com/devicetree-org/devicetree-specification/releases/tag/v0.3
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Nishanth Menon <nm@ti.com>
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Add u-boot,dm-spl tag in the pinmux device tree node, required for MMCSD1
subsystem.
Fixes: b6059ddc45b9 ("arm: dts: k3-am642: Add r5 specific dt support")
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
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USB nodes were mistakenly disabled in
commit 942853dd96df ("arm: dts: Resync BeagleBone device trees")
This commit is to fix the following issue:
starting USB...
No working controllers found
USB is stopped. Please issue 'usb start' first.
starting USB...
No working controllers found
Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=0782e8572ce43f521ed6ff15e4a7ab9aa5acdc85
Fixes: 942853dd96df ("arm: dts: Resync BeagleBone device trees")
Signed-off-by: Matwey V. Kornilov <matwey.kornilov@gmail.com>
Reviewed-by: Paul Barker <paul.barker@sancloud.com>
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Since mvpp2 is using the new mdio driver and the cp110 has been
synced with the linux upstream, the mdio has to enabled in the
device tree file.
This is missing for some device tree files and therefore the
network cards do not come online.
Signed-off-by: Sven Auhagen <sven.auhagen@voleatech.de>
Reviewed-by: Stefan Roese <sr@denx.de>
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SHA512_ALGO was used as a "either SHA512 or SHA384", although the
implementations of these two algorithms share a majority of code.
From a Kconfig interface perspective, it makes sense to present two
distinct options. This requires #ifdefing out the SHA512
implementation from sha512.c. The latter doesn't make any sense.
It's reasonable to say in Kconfig that SHA384 depends on SHA512, and
seems to be the more polite way to handle the selection.
Thus, automatically select SHA512 when SHA384 is enabled.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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We usually use a space in function declaration, rather than a tab.
Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
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