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2021-08-09Merge tag 'u-boot-imx-20210809' of ↵Tom Rini69-142/+7723
https://source.denx.de/u-boot/custodians/u-boot-imx u-boot-imx-20210809 - new SOC: add support for imx8ulp - Toradex fixes for colibri (vf / imx6 / imx7 / imx8x) - convert to DM for mx28evk - Fixes for Gateworks ventana boards CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/8639
2021-08-09imx: cmd: use struct cmd_tblPeng Fan2-2/+2
cmd_tbl_t is removed, need use struct cmd_tbl Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09arm: imx: add i.MX8ULP EVK supportPeng Fan4-0/+273
Add i.MX8ULP EVK basic support, support SD/I2C/ENET/LPUART Log as below: I would keep some debug info for now, and after we move to be stable and production launch, we could drop that. U-Boot SPL 2021.07-rc4-00164-gb800e19a6b (Jun 29 2021 - 10:23:30 +0800) Normal Boot upower_init: soc_id=48 upower_init: version:11.11.6 upower_init: start uPower RAM service user_upwr_rdy_callb: soc=b user_upwr_rdy_callb: RAM version:12.6 Turn on switches ok Turn on memories ok Clear DDR retention ok Poll for freq_chg_req on SIM register and change to F1 frequency. Poll for freq_chg_req on SIM register and change to F0 frequency. Poll for freq_chg_req on SIM register and change to F1 frequency. Poll for freq_chg_req on SIM register and change to F2 frequency. Poll for freq_chg_req on SIM register and change to F1 frequency. Poll for freq_chg_req on SIM register and change to F2 frequency. complete De-Skew PLL is locked and ready WDT: Not found! Trying to boot from BOOTROM image offset 0x8000, pagesize 0x200, ivt offset 0x0 Load image from 0x3a800 by ROM_API NOTICE: BL31: v2.4(release):imx_5.10.35_2.0.0_imx8ulp_er-10-gf37e59b94 NOTICE: BL31: Built : 01:56:58, Jun 29 2021 NOTICE: upower_init: start uPower RAM service NOTICE: user_upwr_rdy_callb: soc=b NOTICE: user_upwr_rdy_callb: RAM version:12.6 U-Boot 2021.07-rc4-00164-gb800e19a6b (Jun 29 2021 - 10:23:30 +0800) CPU: Freescale i.MX8ULP rev1.0 at 744 MHz Reset cause: POR Boot mode: Single boot Model: FSL i.MX8ULP EVK DRAM: 2 GiB MMC: FSL_SDHC: 0, FSL_SDHC: 2 Loading Environment from MMC... *** Warning - bad CRC, using default environment In: serial@293a0000 Out: serial@293a0000 Err: serial@293a0000 Net: Warning: ethernet@29950000 (eth0) using random MAC address - 96:35:88:62:e0:44 eth0: ethernet@29950000 Hit any key to stop autoboot: 0 Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09arm: dts: add i.MX8ULP dtsiPeng Fan2-0/+1706
Add i.MX8ULP dtsi Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09imx8ulp: add upower api supportPeng Fan6-0/+948
Add upower api support, this is modified from upower firmware exported package. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09imx8ulp: move struct mu_type to common headerPeng Fan1-0/+25
Move struct mu_type to common header to make it reusable by upower and S400 Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09imx8ulp: Add workaround for eMMC bootYe Li2-0/+17
When booting from boot part1/2, the image offset should be 0, but ROM has a bug to return 0x8000. Has to workaround the issue before ROM fix it. Use a ROM function to know boot from emmc boot part or user part So we can set the image offset accordingly. Signed-off-by: Ye Li <ye.li@nxp.com>
2021-08-09imx8ulp: Use DGO_GP5 to get boot configYe Li1-1/+1
Since CMC1 MR0 only reflects high 16 bits boot cfg used for AP domian, it does not connect to low 16 bits for RTD. So we can't get the correct boot mode. Change to use DGO_GP5 of SEC_SIM which is set by ROM. Signed-off-by: Ye Li <ye.li@nxp.com>
2021-08-09imx8ulp: soc: correct reset causePeng Fan1-7/+3
The CMC1 SRS reflects the current reset cause, not SSRS. Then you could get "Reset cause: WARM-WDG" when issue reset in U-Boot. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09arm: imx8ulp: add iomuxc supportPeng Fan2-1/+137
Add i.MX8ULP iomuxc support Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09arm: imx8ulp: add dummy imx_get_mac_from_fusePeng Fan1-0/+5
Add imx_get_mac_from_fuse for enet build pass Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09arm: imx8ulp: Allocate DCNANO and MIPI_DSI to AD domainYe Li1-0/+2
Configure DCNANO and MIPI_DSI to be controlled by AD for single boot Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09arm: iMX8ULP: Add boot device relevant functionsYe Li2-0/+85
Read from ROM API to get current boot device. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09arm: imx8ulp: Probe the S400 MU device in arch initYe Li1-1/+34
Need probe the S400 MU device in arch_cpu_init_dm, so we can use S400 API in u-boot Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09imx8ulp: unify rdc functionsPeng Fan3-173/+317
Unify rdc function to rdc.c Update soc.c to use new rdc function Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09arm: imx8ulp: release trdc and assign lpav from RTD to APDPeng Fan1-1/+103
Rlease LPAV from RTD to APD Release gpu2D/3D to APD Set TRDC MBC2 MEM1 for iomuxc0 access Since upower depends AP/M33 SW to configure IOMUX for its PMIC i2c and MODE pins. we have to open iomuxc0 access for A35 core (domain 7) in single boot. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com>
2021-08-09arm: imx8ulp: add trdc release requestPeng Fan1-9/+17
Add TRDC release request, then we could configure resources to be accessible by A35 Domain. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09arm: imx8ulp: add rdc supportPeng Fan3-1/+147
There is xrdc inside i.MX8ULP, we need to configure permission to make sure AP non-secure world could access the resources. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09arm: imx8ulp: release and configure XRDC at early phaseYe Li3-8/+98
Since S400 will set the memory of SPL image to R/X. We can't write to any data in SPL image. 1. Set the parameters save/restore only for u-boot, not for SPL. to avoid write data. 2. Not use MU DM driver but directly call MU API to send release XRDC to S400 at early phase. 3. Configure the SPL image memory of SRAM2 to writable (R/W/X) Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09drivers: misc: s400_api: Update API for fuse read and writeYe Li1-1/+6
Add API to support fuse read and write Signed-off-by: Ye Li <ye.li@nxp.com>
2021-08-09drivers: misc: imx8ulp: Update S400 API for release RDCYe Li1-1/+1
The RDC API is updated to add a field for XRDC or TRDC Signed-off-by: Ye Li <ye.li@nxp.com>
2021-08-09drivers: misc: imx8ulp: Add S400 API for image authenticationYe Li1-1/+7
Add S400 API for image authentication Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09arm: imx8ulp: Update the reset vector in u-bootYe Li1-13/+22
Because we have set reset vector to ATF in SPL, have to set it back to ROM for any reset in u-boot Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09arm: imx8ulp: disable wdog3Peng Fan1-1/+35
Disable wdog3 which is configured by ROM Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09arm: imx8ulp: Enable full L2 cache in SPLYe Li1-0/+34
SRAM2 is half L2 cache and default to SRAM after system boot. To enable the full l2 cache (512KB), it needs to reset A35 to make the change happen. So re-implement the jump entry function in SPL: 1. configure the core0 reset vector to entry (ATF) 2. enable the L2 full cache 3. reset A35 So when core0 up, it runs into ATF. And we have 512KB L2 cache working. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09arm: imx8ulp: soc: Change to use CMC1 to get bootcfgYe Li1-1/+1
CMC1 also has a MR register for bootcfg Signed-off-by: Ye Li <ye.li@nxp.com>
2021-08-09arm: imx8ulp: add clock supportPeng Fan9-4/+1558
Add i.MX8ULP clock support Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09driver: misc: Add MU and S400 API to communicate with SentinelYe Li2-0/+35
Add MU driver and S400 API. Need enable MISC driver to work Signed-off-by: Ye Li <ye.li@nxp.com>
2021-08-09arm: imx: move container Kconfig under mach-imxPeng Fan2-13/+13
Since i.MX8 and i.MX8ULP reuse common container, so move the Kconfig public to both. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09arm: imx8ulp: add container supportYe Li7-47/+177
i.MX8ULP support using ROM API to load container image, it use same ROM API as i.MX8MN/MP, and use same container format as i.MX8QM/QXP. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09arm: imx: parse-container: guard included header filesPeng Fan1-0/+2
Guard included sci.h with CONFIG_AHAB_BOOT to avoid build failure for i.MX8ULP Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09arm: imx8: Move container image header file to mach-imxYe Li5-4/+4
Since the container is shared among i.MX platforms, move its header file to mach-imx Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09arm: imx8: Move container parser and image to mach-imx common folderYe Li4-3/+4
Since we will re-use the container parser on imx8ulp, move the codes to mach-imx Signed-off-by: Ye Li <ye.li@nxp.com>
2021-08-09arm: imx: basic i.MX8ULP supportPeng Fan12-4/+514
Add basic i.MX8ULP support For the MMU part, Using a simple way the calculate the MMU size to avoid default heavy calcaulation. And align address and size in the table settings to 2MB or 4GB as much as possible. So we can reduce the 4K page allocations in MMU table which will spends much time in create the page table Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09imx: imx8ulp: add get reset causePeng Fan1-0/+69
Add get reset cause function to show what triggerred reset. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09arm: imx8ulp: support print cpu infoPeng Fan2-0/+61
Support print cpu info. the clock function has not been added, it will be added in following patches. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09arm: imx: sys_proto: move boot mode define to common headerPeng Fan2-9/+10
These defines could be reused by i.MX8ULP, so move them to common header. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09arm: imx: add i.MX8ULP cpu type and helperPeng Fan4-0/+27
Add i.MX8ULP cpu type and helpers. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09arm: imx: add i.MX8ULP basic Kconfig optionPeng Fan2-0/+27
Add i.MX8ULP related basic Kconfig option, which will be used later. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-08-09mx28evk: Convert to driver modelFabio Estevam2-0/+11
Make the conversion to driver model as it is mandatory. Successfully tested booting Linux from the SD card. Dropped support for networking and splash screen as these need to be properly converted to DM and tested. Signed-off-by: Fabio Estevam <festevam@gmail.com>
2021-08-09board: ge: bx50v3: Add PCIe reset to DTSebastian Reichel1-0/+10
Add PCIe reset gpio to the Bx50v3 devicetree and get get rid of CONFIG_PCIE_IMX_PERST_GPIO. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
2021-08-09board: gateworks: venice: add imx8mm-gw7902 supportTim Harvey3-0/+1008
The GW7902 is based on the i.MX 8M Mini / Nano SoC featuring: - LPDDR4 DRAM - eMMC FLASH - Gateworks System Controller - LTE CAT M1 modem - USB 2.0 HUB - M.2 Socket with USB2.0, PCIe, and dual-SIM - IMX8M FEC - PCIe based GbE - RS232/RS485/RS422 serial transceiver - GPS - CAN bus - WiFi / Bluetooth - MIPI header (DSI/CSI/GPIO/PWM/I2S) - PMIC Do the following to add support for it: - add dts - add PMIC config Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2021-08-09arm: dts: imx8mm-venice-gw7901: use common u-boot dtsiTim Harvey1-34/+1
Use the common imx8mm-u-boot.dtsi Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2021-08-09arm: dts: imx8mm-venice-gw700x: fix fifo-depth phy propsTim Harvey1-2/+1
Replace the deprecated 'tx-fifo-depth' and 'rx-fifo-depth' properties not supported by U-Boot drivers/net/phy/dp83867.c with the proper 'ti,fifo-depth' property. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2021-08-09arm: dts: imx8mm-venice-gw71xx: fix USB OTG VBUSTim Harvey1-2/+3
The GW71xx has a USB Type-C connector with USB 2.0 signaling. GPIO1_12 is the power-enable to the TPS25821 Source controller and power switch responsible for monitoring the CC pins and enabling VBUS. Therefore GPIO1_12 must always be enabled and the vbus output enable from the IMX8MM can be ignored. To fix USB OTG VBUS enable a pull-up on GPIO1_12 to always power the TPS25821 and change the regulator output to GPIO1_10 which is unconnected. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2021-08-09imx: ventana: remove hard-coded USB OTG pinmuxTim Harvey4-0/+4
pinmux is now done via dt. Add missing OTG_OC pinmux for boards that use it. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2021-08-09imx: ventana: fix UMS supportTim Harvey12-24/+24
The Gateworks Ventana boards have always had usb0=usbh1 and usb1=usbotg because OTG is often subloaded on these boards and a bit in the EEPROM which flagging that OTG is subloaded is used to remove the dt node via the alias. U-Boot DM_USB UMS requires the usb0 alias be assigned to the usbotg so fix the usb0 alias in order for UMS to work. Fixes 72c46327f03f: ("imx: ventana: enable dm support for USB") Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2021-08-08Revert "arm: bootm: Disable LMB reservation for command line and board info ↵Jan Kiszka1-2/+0
on arm64" This reverts commit 2359fa7a87848626bcbd3399e92c657595880cd7. While the goal is valid and there is surely unused memory in that area, we also have a lot of crucial things still located at the top-of-memory while running lmb_alloc_base. Such things are the page table (tlb_addr), relocated U-Boot and the active stack. Possibly more. So this patch was premature, we will need relocations of those things first if we want to use the range. Fixes booting on the IOT2050, but likely also on other boards. It got stuck on relocating the FDT - over the relocated U-Boot code. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
2021-08-08ARM: renesas: Turn on PIE for Gen3Marek Vasut1-0/+1
Turn on PIE, so that the U-Boot binary can be started from any arbitrary location in DRAM instead of a predefined fixed one. Note that this patch is not setting SYS_TEXT_BASE=0x0 yet, since that triggers relocation bugs in env code that are yet to be fixed. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Biju Das <biju.das.jz@bp.renesas.com> Cc: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
2021-08-06pci: ppc: Drop ftpci100 driverSimon Glass1-2/+0
This is not used in U-Boot at present. Drop it and related config options. Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.2.3 (git 2.39.0) at 2024-08-21 21:47:41 +0300