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2020-08-08board: presidio: add LED supportJway Lin1-0/+31
Add LED support for Cortina Access Presidio Engineering Board Signed-off-by: Jway Lin <jway.lin@cortina-access.com> Signed-off-by: Alex Nemirovsky <alex.nemirovsky@cortina-access.com> Reviewed-by: Simon Glass <sjg@chromium.org> CC: Simon Glass <sjg@chromium.org>
2020-08-06board_f: ppc: Factor out ppc-specific bdinfo setupOvidiu Panait1-0/+25
Factor out ppc-specific bdinfo setup from generic init sequence to arch_setup_bdinfo in arch/powerpc/lib/bdinfo.c. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
2020-08-06board_f: m68k: Factor out m68k-specific bdinfo setupOvidiu Panait1-0/+21
Factor out m68k-specific bdinfo setup to arch_setup_bdinfo in arch/m68k/lib/bdinfo.c. Also, use if(IS_ENABLED()) instead of #ifdef where possible. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
2020-08-06board_f: Factor out bdinfo bi_mem{start, size} to setup_bdinfoOvidiu Panait4-9/+23
Move all assignments to gd->bd->bi_mem{start,size} to generic code in setup_bdinfo. Xtensa architecture is special in this regard as it defines its own handling of gd->bd->bi_mem{start,size} fields. In order to avoid defining a weak SDRAM function, let arch_setup_bdinfo overwrite the generic flags. For ARC architecture, remove ARCH_EARLY_INIT_R from Kconfig since it is not needed anymore. Also, use gd->ram_base to populate bi_memstart to avoid an ifdef. Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com> Acked-by: Alexey Brodkin <abrokdin@synopsys.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-06cmd: bdinfo: Move sram info prints to generic codeOvidiu Panait2-8/+0
bi_sramstart and bi_sramsize are generic members of the bd_info structure, so move the m68k/powerpc-specific prints to generic code. Also, print them only if SRAM support is enabled via CONFIG_SYS_HAS_SRAM. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
2020-08-06arm: mvebu: Update CRS305-1G-4S board flash layoutLuka Kovacic1-5/+5
Update the MikroTik CRS305-1G-4S flash layout to support redundant UBI partitions. Additionally enable the UBI commands in crs305-1g-4s_defconfig. Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Jakov Petrina <jakov.petrina@sartura.hr> Reviewed-by: Stefan Roese <sr@denx.de>
2020-08-06arm: mvebu: Add CRS328-4C-20S-4S boardLuka Kovacic5-0/+185
MikroTik CRS328-4C-20S-4S board has a switch chip with an integrated Marvell Prestera 98DX3236 CPU. This commit includes two board variants, namely the factory default one and a Bit variant. The Bit board variant has a bigger Macronix flash. Add basic U-Boot, UART and SPI flash support. Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Jakov Petrina <jakov.petrina@sartura.hr> Reviewed-by: Stefan Roese <sr@denx.de>
2020-08-06arm: mvebu: Add CRS326-24G-2S boardLuka Kovacic5-0/+185
MikroTik CRS326-24G-2S board has a switch chip with an integrated Marvell Prestera 98DX3236 CPU. This commit includes two board variants, namely the factory default one and a Bit variant. The Bit board variant has a bigger Macronix flash. Add basic U-Boot, UART and SPI flash support. Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Jakov Petrina <jakov.petrina@sartura.hr> Reviewed-by: Stefan Roese <sr@denx.de>
2020-08-06arm: mvebu: Add CRS305-1G-4S Bit boardLuka Kovacic2-0/+44
MikroTik CRS305-1G-4S Bit board has a switch chip with an integrated Marvell Prestera 98DX3236 CPU. The Bit board variant is added, which has a bigger Macronix flash. Add basic U-Boot, UART and Winbond SPI flash support. Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Jakov Petrina <jakov.petrina@sartura.hr> Reviewed-by: Stefan Roese <sr@denx.de>
2020-08-05Merge https://gitlab.denx.de/u-boot/custodians/u-boot-shTom Rini2-1/+30
- r2dplus updates
2020-08-05ARM: add Kconfig option for PSCI 0.1Icenowy Zheng1-0/+4
We still have some platforms that only implements functionalities in PSCI 0.1 (e.g. Allwinner ARMv7 SoCs). Add a Kconfig option for exporting only PSCI 0.1. The code to export PSCI 0.1 is still available and gets activated by this patch. In addition, default ARCH_SUNXI U-Boot PSCI implementation to export PSCI 0.1, to fix poweroff/reboot regression on Allwinner multi-core ARMv7 SoCs. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2020-08-05arm: Add SPL build check to SPL early bss clearBrian Moyer1-5/+5
SPL_CLEAR_BSS is called regardless of build type if CONFIG_SPL_EARLY_BSS is defined. Add a guard for CONFIG_SPL_BUILD to fix. Signed-off-by: Brian Moyer <bdm310@gmail.com>
2020-08-05cmd: add clone commandJohn Chau1-0/+1
This patch adds a feature for block device cloning similar to dd command, this should be useful for boot-strapping a device where usb gadget or networking is not available. For instance one can clone a factory image into a blank emmc from an external sd card. Signed-off-by: John Chau <john@harmon.hk>
2020-08-04Merge tag 'u-boot-imx-20200804' of ↵Tom Rini16-95/+436
https://gitlab.denx.de/u-boot/custodians/u-boot-imx For 2020.10 ----------- - fixes for Toradex board - fix warnings from previous PR - HAB: reset instead of panic after failure - new board: MYiR Tech MYS-6ULX - mx6cuboxi: use OF_PLATDATA - further changes for DM Travis: https://travis-ci.org/github/sbabic/u-boot-imx/builds/714513163
2020-08-04Merge https://gitlab.denx.de/u-boot/custodians/u-boot-riscvTom Rini2-0/+25
- add DM based reset driver for SiFive SoC's.
2020-08-04Merge tag 'mips-pull-2020-08-03' of ↵Tom Rini3-3/+90
https://gitlab.denx.de/u-boot/custodians/u-boot-mips - doc: fix qemu-mips build instructions - MIPS: add GPIO, CLK and SPI drivers for Octeon MIPS64
2020-08-04mscc: Drop dm.h header fileSimon Glass5-15/+0
This header file should not be included in other header files. Remove it from each one and use a forward declaration instead. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-08-04mediatek: Drop dm.h header fileSimon Glass1-1/+1
This header file should not be included in other header files. Remove it and use a forward declaration instead. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-08-04thermal: Drop dm.h header fileSimon Glass1-0/+1
This header file should not be included in other header files. Remove it and use a forward declaration instead. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-08-04sf: Drop dm.h header file from spi_flash.hSimon Glass3-0/+3
This header file should not be included in other header files. Remove it and use a forward declaration instead. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-08-04sifive: reset: add DM based reset driver for SiFive SoC'sSagar Shrikant Kadam1-0/+13
PRCI module within SiFive SoC's has register with which we can reset the sub-systems within the SoC. The resets to DDR and ethernet sub systems within FU540-C000 SoC are active low, and are hold low by default on power-up. Currently these are directly asserted within prci driver via register read/write. With the DM based reset driver support here, we bind the reset driver with clock (prci) driver and assert the reset signals of both sub-system's appropriately. Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com> Reviewed-by: Pragnesh Patel <Pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com>
2020-08-04fu540: dtsi: add reset producer and consumer entriesSagar Shrikant Kadam1-0/+12
The resets to DDR and ethernet sub-system are connected to PRCI device reset control register, these reset signals are active low and are held low at power-up. Add these reset producer and consumer details needed by the reset driver. Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-08-03mips: octeon: Update Octeon KconfigStefan Roese1-2/+4
This patch selects DM_SPI & DM_I2C for MIPS Octeon. DM_GPIO, DM_SERIAL and DM_ETH are already selected. Additionally the selections are now alphabetically sorted. Signed-off-by: Stefan Roese <sr@denx.de>
2020-08-03mips: octeon: mrvl, octeon-ebb7304.dts: Add SPI flash DT nodeStefan Roese1-0/+9
Add the SPI flash DT node for the EBB7304. Signed-off-by: Stefan Roese <sr@denx.de>
2020-08-03mips: octeon: mrvl,cn73xx.dtsi: Add SPI DT nodeStefan Roese1-0/+10
Add the Octeon SPI DT node to the dtsi file. Signed-off-by: Stefan Roese <sr@denx.de>
2020-08-03mips: octeon: dts: Add Octeon clock driver DT nodesStefan Roese2-1/+11
This patch adds the DT nodes for the Octeon clock support via the common clk_ API. Signed-off-by: Stefan Roese <sr@denx.de>
2020-08-03mips: octeon: dts: Add I2C DT nodesStefan Roese2-0/+30
Add I2C DT nodes to the Octeon dts / dtsi files. Signed-off-by: Stefan Roese <sr@denx.de>
2020-08-03mips: octeon: mrvl,cn73xx.dtsi: Add GPIO DT nodesStefan Roese1-0/+26
Add the Octeon GPIO DT node to the dtsi file. Signed-off-by: Stefan Roese <sr@denx.de>
2020-08-03ARM: imx: hab: panic on authentication failureMarek Vasut1-4/+2
Instead of hang()ing the system and thus disallowing any automated recovery possibility from a HAB authentication failure, panic() . The panic() function can be configured to hang() the system after printing an error message, however the default is to reset the system instead. This allows redundant boot to work correctly. In case the primary or secondary image cannot be authenticated, the system reboots and bootrom can try to start the other one. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2020-08-03imx: Add MYiR Tech MYS-6ULX supportParthiban Nallathambi6-0/+295
MYS-6ULX is single board computer (SBC) comes with eMMC or NAND based on imx6ULL SoC from NXP and provision for expansion board. This commit adds support only for SBC with NAND. CPU: Freescale i.MX6ULL rev1.1 528 MHz (running at 396 MHz) CPU: Commercial temperature grade (0C to 95C) at 45C Reset cause: WDOG Model: MYiR i.MX6ULL MYS-6ULX Single Board Computer with NAND Board: MYiR MYS-6ULX 6ULL Single Board Computer DRAM: 256 MiB NAND: 256 MiB MMC: FSL_SDHC: 0 In: serial@2020000 Out: serial@2020000 Err: serial@2020000 Net: FEC0 Working: - Eth0 - MMC/SD - NAND - UART 1 - USB host Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
2020-08-03Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86Tom Rini7-11/+72
- ApolloLake: add u64 parameters support for FSP2 bindings - ApolloLake: add missing parameters to support full configuration of the latest FSP MR6 release - Append appropriate suffixes in various assembly codes
2020-08-03x86: call32: Append appropriate suffixesAndy Shevchenko1-3/+2
Assembler is not happy: arch/x86/cpu/call32.S: Assembler messages: arch/x86/cpu/call32.S:36: Warning: no instruction mnemonic suffix given and no register operands; using default for `retf' Fix this by adding appropriate suffixes to the assembler commands. Fixes: 6f92ed8f1abf ("x86: Add a way to call 32-bit code from 64-bit mode") Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-08-03x86: sipi_vector: Append appropriate suffixesAndy Shevchenko1-3/+3
Assembler is not happy: arch/x86/cpu/sipi_vector.S: Assembler messages: arch/x86/cpu/sipi_vector.S:134: Warning: no instruction mnemonic suffix given and no register operands; using default for `cmp' arch/x86/cpu/sipi_vector.S:139: Warning: no instruction mnemonic suffix given and no register operands; using default for `bts' arch/x86/cpu/sipi_vector.S:157: Warning: no instruction mnemonic suffix given and no register operands; using default for `cmp' Fix this by adding appropriate suffixes to the assembler commands. Fixes: 45b5a37836d5 ("x86: Add multi-processor init") Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-08-03arch: x86: apl: Update FSP parametersBernhard Messerklinger3-2/+35
Add missing parameters to support full configuration of the latest FSP MR6 release. Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-03x86: apl: fsp_bindings: Add support for u64 parametersBernhard Messerklinger2-0/+29
Add FSP_UINT64 read support as preparation for FSP-M and FSP-S parameter update. Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-03x86: irq: Fix some typosWolfgang Wallner1-3/+3
Fix some typos in arch/x86/include/asm/irq.h. Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-08-02sh: r2dplus: Add SCIF1 to the basic DTMarek Vasut1-0/+23
Add simple DT and clock bindings to r2dplus DT to permit U-Boot to bind the SCIF driver via DT probing instead of hard-coded config options. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2020-08-02sh: Set gd->malloc_base if MALLOC_F_LEN is setMarek Vasut1-1/+7
The gd->malloc_base must be set before the C runtime if the MALLOC_F_LEN is non-zero, otherwise we hit assertion in dlmalloc.c initf_malloc(). So set it. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2020-08-01efi_loader: use CONFIG_STACK_SIZE in the UEFI sub-systemHeinrich Schuchardt2-25/+0
The Kconfig symbol CONFIG_STACK_SIZE is used both by ARM and Microblaze with the same meaning. Move it to menu 'General setup' so that we can use it for all architectures. Use the value of CONFIG_STACK_SIZE instead of a hard coded 16 MiB value for reserving memory in the UEFI sub-system. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-08-01x86: rename CONFIG_STACK_SIZEHeinrich Schuchardt2-2/+2
Configuration variables should have the same meaning independent of the architecture. x86 and ARM both use CONFIG_STACK_SIZE: * x86: U-Boot's runtime stack size during reboot * ARM: max stack size that can be used by U-Boot Rename the x86 configuration variable to CONFIG_STACK_SIZE_REBOOT Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-07-30Merge tag 'dm-pull-28jul20' of git://git.denx.de/u-boot-dmTom Rini27-128/+230
Use binman instead of one of the Rockchip build scripts Refactor to allow any arch to create SPI-flash images New button uclass
2020-07-29Merge https://gitlab.denx.de/u-boot/custodians/u-boot-stmTom Rini25-183/+1572
- fix SPL boot issue due to early dbgmcu_init() call - fix SPL boot issue due to dcache memory region configuration - add support of CONFIG_ENV_IS_IN_MMC - add specific SD/eMMC partition for U-Boot enviromnent - enable env in SPL - use "env info -q" to remove log during boot - remove env location override for dh_stm32mp1 - update management of misc_read - check result of find_mmc_device in stm32prog - use regulator_set_enable_if_allowed for disabling vdd supply in usbphyc - enable CMD_ADTIMG flag to handle Android images - device tree alignment with Linux Kernel v5.8-rc1 - remove hnp-srp-disable for usbotg on dk1 - add reset support to uart nodes on stm32mp15x - use correct weak function name spl_board_prepare_for_linux - use cd-gpios for ST and DHSOM boards - add seeed studio odyssey-stm32mp157c board support - move ethernet PHY into SoM DT - add DHSOM based DRC02 board support
2020-07-29arch: arm: use dt and UCLASS_SYSCON to get gic lpi detailsRayagonda Kokatanur4-36/+61
Use device tree and UCLASS_SYSCON driver to get Generic Interrupt Controller (GIC) lpi address and maximum GIC redistributors count. Also update Kconfig to select REGMAP and SYSCON when GIC_V3_ITS is enabled. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-07-29arch: arm: use dt and UCLASS_IRQ to get gic detailsRayagonda Kokatanur1-7/+66
Use device tree and UCLASS_IRQ driver to get following Generic Interrupt Controller (GIC) details, -GIC Distributor interface (GICD) base address and -GIC Redistributors (GICR) base address. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-07-29gpio: do not include <asm/arch/gpio.h> on TARGET_BCMNS3Rayagonda Kokatanur1-1/+2
As no gpio.h is defined for this architecture, to avoid compilation failure, do not include <asm/arch/gpio.h> for arch bcmns3. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-07-29board: ns3: define ddr memory layoutRayagonda Kokatanur1-0/+23
Add both DRAM banks memory information and the corresponding MMU page table mappings. Signed-off-by: Bharat Kumar Reddy Gooty <bharat.gooty@broadcom.com> Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-07-29board: ns3: add api to save boot parameters passed from BL31Abhishek Shah2-0/+35
Add API to save boot parameters passed from BL31 Use assembly implementation of save_boot_params instead of c function. Because generally ATF does not set up SP_EL2 on exiting. Thus, usage of a C function immediately after exiting with no stack setup done by ATF explicitly, may cause SP_EL2 to be not sane, which in turn causes a crash if this boot was not lucky to get an SP_EL2 in valid range. Replace C implementation with assembly one which does not use stack this early, and let u-boot to set up its stack later. Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com> Signed-off-by: Rajesh Ravi <rajesh.ravi@broadcom.com> Signed-off-by: Vladimir Olovyannikov <vladimir.olovyannikov@broadcom.com> Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-07-29arm: cpu: armv8: add L3 memory flush supportRayagonda Kokatanur3-0/+95
Add L3 memory flush support for NS3. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-07-29board: ns3: add support for Broadcom Northstar 3Rayagonda Kokatanur4-0/+70
Add support for Broadcom Northstar 3 SoC. NS3 is a octo-core 64-bit ARMv8 Cortex-A72 processors targeting a broad range of networking applications. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-07-29board: mediatek: Add support for UniElec U7623 boardDavid Woodhouse2-0/+212
This is an MT7623A-based board, very similar to the Banana Pi R2. http://www.unielecinc.com/q/news/cn/p/product/detail.html?qd_guid=OjXwKCaRlN Signed-off-by: David Woodhouse <dwmw2@infradead.org>
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