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2023-09-14Merge tag 'JH7110_515_SDK_v5.7.3' into vf2-develVF2_v3.7.5VF2_6.1_v3.7.5Andy Hu1-2/+2
2023-09-11riscv: dts: Add link state register to PCIe syscon nodes.Kevin.xie1-2/+2
Signed-off-by: Kevin.xie <kevin.xie@starfivetech.com>
2023-09-07dts: usb: add starfive,usb2-only propertyMinda Chen1-0/+1
For the codes has been changed, Add starfive,usb2-only property. Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
2023-09-07Merge tag 'JH7110_515_SDK_v5.7.2' into vf2-develAndy Hu1-0/+1
2023-09-05dts: usb: Add starfive,usb2-only to zeroMinda Chen1-0/+1
Add starfive,usb2-only to zero in evb board. Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
2023-08-31Merge tag 'JH7110_515_SDK_v5.7.0' into vf2-develAndy Hu2-4/+23
2023-08-25dts: usb: Add USB 3.0 clock dts.Minda Chen1-0/+15
Add evb USB 3.0 clock dts. Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
2023-08-25dts: starfive: devkits: Update usb device tree nodeYanhong Wang1-4/+8
Updated USB Device Tree Node to support USB Device functionality and is consistent with Kernel. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
2023-07-28Merge tag 'JH7110_515_SDK_v5.4.3' into vf2-develAndy Hu1-0/+2
2023-07-28riscv: dts: starfive: limit cclk_in frequencyWilliam Qiu1-0/+2
The frequency of cclk_in is limited to 50M, so that it does not do internal part frequency and goes by-pass mode. And delete syscon node. Signed-off-by: William Qiu <william.qiu@starfivetech.com>
2023-07-28riscv: dts: starfive: limit cclk_in frequencyWilliam Qiu1-0/+4
The frequency of cclk_in is limited to 50M, so that it does not do internal part frequency and goes by-pass mode. And delete syscon node. Signed-off-by: William Qiu <william.qiu@starfivetech.com>
2023-07-27Merge tag 'JH7110_515_SDK_v5.4.2' into vf2-develAndy Hu1-6/+13
2023-07-26gpio: starfive: Add SET_DS/SET_PULL/SET_SLEW supportSamin Guo1-1/+23
SET_DS/SET_PULL/SET_SLEW can configure the properties of the GPIO Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2023-07-26dts: starfive: Enable pcie0 and set cdns3 mode to deviceMinda Chen1-2/+2
Enable pcie0 to active usb-host. And set cdns3 to device mode. Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
2023-07-20Merge tag 'JH7110_515_SDK_v5.4.1' into vf2-develAndy Hu1-4/+4
2023-07-20board: starfive: evb: use dram_init in splSamin Guo2-1/+7
dram_init call fdtdec_setup_mem_size_base, so starfive_ddr.c do not need it. Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2023-07-20board: starfive: vf2: Modify arch/riscv/cpu/jh7110/spl.cSamin Guo1-7/+0
For integration with other Borad, move I2C to a board-level file Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2023-07-20Merge branch 'CR_6604_1G_DDR_SYNC_samin.guo' into 'jh7110-master'andy.hu1-40/+10
CR6604：dram: jh7110: sync from devkits/vf2 See merge request sdk/u-boot!59
2023-07-19dram: jh7110: remove resize-ddr functionSamin Guo1-40/+10
The resize-ddr should be board-level code Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2023-07-18riscv: dts: starfive: jh7110: replace mipi&hdmi nodeKeith Zhao1-4/+4
replace mipi&hdmi node , hdmi logo will start begin mipi Signed-off-by: Keith Zhao <keith.zhao@starfivetech.com>
2023-07-18dram: jh7110: remove resize-ddr functionSamin Guo1-40/+10
The resize-ddr should be board-level code Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2023-07-10dram: starfive: jh7110: Add 1G supportSamin Guo1-0/+1
add 1G DDR tuning cfg Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2023-07-10dram: jh7110: Add CONFIG_ID_EEPROM to determine if EEPROM is availableSamin Guo1-18/+26
When eeprom reads, you need to determine whether eeprom supports it. Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2023-07-10dram: jh7110: Macro definitions STARFIVE_JH7110_EEPROM_DDRINFO_OFFSETSamin Guo1-1/+2
In order to read DDR info from eeprom. Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2023-07-10dram: starfive: jh7110: Add 1G supportSamin Guo1-0/+1
add 1G DDR tuning cfg Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2023-07-10dram: jh7110: Add CONFIG_ID_EEPROM to determine if EEPROM is availableSamin Guo1-18/+26
When eeprom reads, you need to determine whether eeprom supports it. Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2023-07-10dram: jh7110: Macro definitions STARFIVE_JH7110_EEPROM_DDRINFO_OFFSETSamin Guo1-1/+2
In order to read DDR info from eeprom. Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2023-06-25dram: jh7110: Add resize DDR info from EEPROM.Samin Guo1-2/+47
sync from vf2 and add resize DDR info from EEPROM Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2023-05-19Merge tag 'JH7110_515_SDK_v5.0.0' into vf2-develAndy Hu1-6/+6
update toolchain to gcc 12.2.0
2023-05-18riscv: dts: starfive: add zicsr_zifencei to riscv,isa stringAndy Hu1-6/+6
Starting from gcc 12.x, csr and fence instructions have been separated from the base I instruction set. special the zicsr_zifencei string to DT riscv,isa string Signed-off-by: Andy Hu <andy.hu@starfivetech.com>
2023-05-12Merge branch 'CR_5042_gmac_phy_delay_ds_samin.guo' into 'vf2-devel'andy.hu1-1/+9
CR5042: riscv: dts: starfive: vf2: add Pad Drive Strength Cfg See merge request sbc/u-boot!49
2023-04-28Merge tag 'JH7110_515_SDK_v4.8.2' into vf2-develAndy Hu6-6/+6
2023-04-24riscv: dts: starfive: vf2: set gmac1 rx delay to 300psSamin Guo1-0/+1
set gmac1 rx delay to 300ps to to match better delays. Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2023-04-24riscv: dts: starfive: vf2: set gmac0 rx delay to 1500psSamin Guo1-1/+2
set gmac0 rx delay to 1500ps to to match better delays. Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2023-04-24riscv: dts: starfive: vf2: add Pad Drive Strength CfgSamin Guo1-0/+6
Increase the drive strength of rx_clk to increase the delay available window. Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2023-04-23board: starfive: copyright: Standardize the copyright formatYanhong Wang6-6/+6
Unify the content format of the copyright section Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
2023-04-20Merge tag 'JH7110_515_SDK_v4.8.1' into vf2-develAndy Hu1-5/+2
version JH7110_515_SDK_v4.8.1 for JH7110 EVB board 1. u-boot: Merge branch 'CR_4747_remove_cycles_pmu_dts_minda' into 'jh7110-master'
2023-04-10dts: pmu: remove pmu dts stall cycles config.Minda Chen1-5/+2
class 8 and class9 cpu stall cycles hwcounter is not supported in U74. delete the configuration. Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
2023-04-07Merge branch 'CR_4563_memcpy_samin.guo' into 'vf2-devel'andy.hu1-7/+24
CR4563: Configure the l2 prefetcher parameter See merge request sbc/u-boot!47
2023-04-07Merge tag 'JH7110_515_SDK_v4.7.0' into vf2-develah1-0/+10
version JH7110_515_SDK_v4.7.0 for JH7110 EVB board 1. #3910: u-boot: update cpu voltage set commands per binning information from OTP 2. #4563: u-boot: configure the l2 prefetcher
2023-04-04riscv: dts: jh7110: Add L2 pretcher configurationSamin Guo1-0/+10
Add L2 pretcher configuration for starfive jh7110 SoC. Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2023-04-03riscv: starfive: jh7110: add check_eeprom_dram_infoSamin Guo1-2/+19
Make sure that the read DDR information is a valid value Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2023-04-03riscv: jh7110: dram: only read a byte data from eeprom.Samin Guo1-6/+6
only read a byte data from eeprom. Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2023-03-30Merge tag 'JH7110_515_SDK_v4.6.0' into vf2-develAndy Hu1-0/+2
1. #4446: u-boot: fix the crash problem when using gpio cmd for pinctrl
2023-03-28riscv: dts: starfive: Add gpio-controller for the gpio nodeHal Feng1-0/+2
Add gpio-controller for node gpio and gpioa. Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2023-03-21display: update hdmi pin configkeith.zhao1-10/+1
delete the hdmi i2c pin which is unused Signed-off-by: keith <keith.zhao@starfivetech.com>
2023-03-20pmic: axp15060pmic reset failkeith.zhao1-55/+4
it is caused by evb pmic module merger to vf2 no need to do this revert it now Signed-off-by: keith <keith.zhao@starfivetech.com>
2023-03-19Merge tag 'JH7110_515_SDK_v4.5.1' into vf2-develAndy Hu2-3/+36
version JH7110_515_SDK_v4.5.1 for JH7110 EVB board 1. #4094: u-boot: update uboot logo display function 2. #3910: u-boot: add 1.1 & 1.02v max cpu voltage to enhance cpu binning voltage type
2023-03-17riscv: dts: starfive: change i2c2 gpio pinkeith.zhao1-4/+4
change i2c2 pin 11,9 to 3,2 , it is diff from evb Signed-off-by: keith <keith.zhao@starfivetech.com>
2023-03-17riscv: support building double-float modulesHeinrich Schuchardt2-3/+27
The riscv32 toolchain for GCC-12 provided by kernel.org contains libgcc.a compiled for double-float. To link to it we have to adjust how we build U-Boot. As U-Boot actually does not use floating point at all this should not make a significant difference for the produced binaries. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
generated by cgit v1.2.3 (git 2.39.0) at 2024-08-10 06:40:12 +0300