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2020-07-25ARM: rmobile: Add Beacon EmbeddedWorks RZG2M Dev KitAdam Ford6-0/+965
The Beacon EmbeddedWorks kit is based on the R8A774A1 SoC also known as the RZ/G2M. The kit consists of a SOM + Baseboard and supports microSD, eMMC, Ethernet, a couple celular radios, two CAN interfaces, Bluetooth and WiFi. Signed-off-by: Adam Ford <aford173@gmail.com>
2020-07-25ARM: dts: r8a774a1: Import DTS from Linux 5.8-rc1Adam Ford1-0/+2787
This patch imports the device tree and required bindings to permit the device tree to build for the R8Z774A1 (RZ/G2M). Signed-off-by: Adam Ford <aford173@gmail.com>
2020-07-25ARM: renesas: Add basic R8A774A1 SupportAdam Ford1-0/+3
In order to build boards based on the R8A774A1, there needs to be a config option from which to enable other drivers and/or flags for this SoC. Signed-off-by: Adam Ford <aford173@gmail.com>
2020-07-24Merge https://gitlab.denx.de/u-boot/custodians/u-boot-riscvTom Rini6-7/+44
- Fix SiFive HiFive Unleashed board booting failure problem. - Enable SiFive fu540 PWM driver. - Support SiFive fu540: SPI boot. - Update OpenSBI used for RISC-V CI testing. - Revert "riscv: Allow use of reset drivers". - Revert "Revert "riscv: sifive: fu540: Add gpio-restart support"". - sysreset: syscon: - Don't assume default value for offset and mask property. - Support value property. - qemu: Add syscon reboot and poweroff support. - Fix SIFIVE debug serial dependency. - Fix linking error when building u-boot-spl with no SMP support. - AE350 use fdtdec_get_addr_size_auto_noparent to parse smc reg. - Make memory node available to SPL in hifive-unleashed-a00-u-boot.dtsi - SiFive fu540 avoid using hardcoded ram base and size.
2020-07-24Revert "Merge tag 'dm-pull-20jul20' of git://git.denx.de/u-boot-dm"Tom Rini18-64/+56
This reverts commit 5d3a21df6694ebd66d5c34c9d62a26edc7456fc7, reversing changes made to 56d37f1c564107e27d873181d838571b7d7860e7. Unfortunately this is causing CI failures: https://travis-ci.org/github/trini/u-boot/jobs/711313649 Signed-off-by: Tom Rini <trini@konsulko.com>
2020-07-24riscv: dts: hifive-unleashed-a00: Make memory node available to SPLBin Meng1-0/+4
Make memory node available to SPL in prepration to updates to SiFive DDR RAM driver to read memory information from DT. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
2020-07-24riscv: Fix linking error when building u-boot-spl with no SMP supportLeo Yu-Chi Liang1-0/+2
Switch off SMP support when building u-boot-spl would cause linking error as follow: undefined reference to 'secondary hart relocate' and 'smp_call_function'. Add macro to wrap up proper code region that needs SMP configuration on. Signed-off by: Leo Liang <ycliang@andestech.com> Cc: rick@andestech.com Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-07-24Revert "riscv: Allow use of reset drivers"Bin Meng1-2/+0
This reverts commit 958a3f464c7f8ef7e10db9feb663e9e80445ce2f. A more appropriate change below is already in mainline. Commit fd31e4fd184f ("riscv: Do not build reset.c if SYSRESET is on") Revert this patch, so that U-Boot can be built successfully for SiFive Fu540 board. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Leo Liang <ycliang@andestech.com>
2020-07-24env: Enable SPI flash env for SiFive FU540Jagan Teki1-0/+13
SPI flash device on HiFive Unleashed has 32MiB Size. This patch adds SPI flash environment after U-Boot proper partition with a size of 128KiB. SPI flash partition layout(32MiB): 0 - 34 : reserved for GPT header 35 - 39 : unused 40 - 2087 : loader1 (SPL, FSBL) 2088 - 10279 : loader2 (U-Boot proper, U-Boot) 10280 - 10535 : environment 10536 - 65494 : rootfs 65528 - 65536 : distro script Note: the loader1 must start from 40th sector even though there are 6 free sectors prior since 40th sector is nearest flash sector boundary.  Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com>
2020-07-24sifive: fu540: Add Booting from SPIJagan Teki1-0/+12
Add booting from SPI for SiFive Unleashed board. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com>
2020-07-24riscv: Make SiFive HiFive Unleashed board boot againBin Meng2-5/+13
Commit 40686c394e53 ("riscv: Clean up IPI initialization code") caused U-Boot failed to boot on SiFive HiFive Unleashed board. The codes inside arch_cpu_init_dm() may call U-Boot timer APIs before the call to riscv_init_ipi(). At that time the timer register base (e.g.: the SiFive CLINT device in this case) is unknown yet. It might be the name riscv_init_ipi() that misleads people to only consider it is related to IPI, but in fact the timer capability is provided by the same SiFive CLINT device that provides the IPI. Timer capability is needed for both UP and SMP. Considering that the original refactor does have benefits, that it makes the IPI code more similar to U-Boot initialization idioms. It also removes some quite ugly macros. Let's do the minimal revert instead of a complete revert, plus a fixes to arch_cpu_init_dm() to consider the SPL case. Fixes: 40686c394e53 ("riscv: Clean up IPI initialization code") Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Tested-by: Leo Liang <ycliang@andestech.com>
2020-07-23Merge tag 'dm-pull-20jul20' of git://git.denx.de/u-boot-dmTom Rini18-56/+64
binman support for FIT new UCLASS_SOC patman switch 'test' command minor fdt fixes patman usability improvements
2020-07-22Merge tag 'u-boot-rockchip-20200722' of ↵Tom Rini30-197/+1379
https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - New rk3326 board: Hardkernel Odroid Go2; - Update board config and dts for RockPI 4/N8/N10; - Update led boot on support for roc-rk3399-pc; - Enable SPI Flash suppor for rk3328 rock64 board; - Update rockchip pcie phy to use generic framework;
2020-07-22arm64: dts: rockchip: Add u-boot, spl-boot-order for ROCKPi N10Jagan Teki1-0/+6
Add u-boot,spl-boot-order for ROCKPi N10, so-that it can able to boot from eMMC and SDMMC in order. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22arm64: dts: rockchip: Add PCIe for RockPI N10Jagan Teki1-2/+38
This patch adds support to enable PCIe for RockPI N10. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22arm: dts: rockchip: Add HDMI out for RockPI N8/N10Jagan Teki3-0/+42
This patch adds support to enable HDMI out for N10 and N8 combinations SBCs. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22ARM: dts: rockchip: Add USB for RockPI N8/N10Jagan Teki3-0/+138
Radxa dalang carrier board has 2x USB 2.0 and 1x USB 3.0 ports. This patch adds support to enable all these USB ports for N10 and N8 combinations SBCs. Note that the USB 3.0 port on RockPI N8 combination works as USB 2.0 OTG since it is driven from RK3288. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22ARM: dts: rockchip: Add usb host0 ohci node for rk3288Jagan Teki1-1/+10
rk3288 and rk3288w have a usb host0 ohci controller. Although rk3288 ohci doesn't actually work on hardware, but rk3288w ohci can work well. So add usb host0 ohci node in rk3288 dtsi and the quirk in ohci platform driver will disable ohci on rk3288. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22arm: dts: rockchip: Sync rk3288 dtsi from linuxSuniel Mahesh1-0/+6
This sync has changes required to use HDMI CEC pin in U-Boot. Sync dts from linux v5.8-rc5 commit: "ARM: dts: rockchip: define the two possible rk3288 CEC pins" (sha1: 838980dd04e994bf81cf104fa01ae60802146b39) Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
2020-07-22ARM: dts: rockchip: Sync ROCKPi N8/N10 dts(i) from LinuxJagan Teki5-136/+104
Sync ROCKPi N8/N10 dts(i) changes from Linux. commit <afd9eb880414> ("ARM: dts: rockchip: Add Radxa Rock Pi N8 initial support") Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
2020-07-22rockchip: Separate the reset cause from display cpuinfoJagan Teki3-9/+18
reset cause is a generic functionality based on the soc cru registers in rockchip. This can be used for printing the cause of reset in cpuinfo or some other place where reset cause is needed.  Other than cpuinfo, reset cause can also be using during bootcount for checking the specific reset cause and glow the led based on the reset cause. So, let's separate the reset cause code from cpuinfo, and add a check to build it for rk3399, rk3288 since these two soc are supporting reset cause as of now. Tested-by: Suniel Mahesh <sunil@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22rockchip: Don't clear the reset status regJagan Teki2-7/+0
reset reason can be used several stages of U-Boot bootloader like SPL, U-Boot proper based on the requirements. Clearing the status register end of get_reset_cause will end up showing the wrong reset cause when it read the second time. For example, if board resets, SPL reads the reset status as RST whereas U-Boot proper reads the status as POR. However, based on the latest testing clearing reset status won't be required for determine the last reset cause or following resets. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22rockchip: tpl: Remove board_early_init_f()Kever Yang1-7/+0
There is no need for board_early_init_f() in TPL, anything like this should goes to SPL. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22rockchip: rk3399: Add weak led_setup()Jagan Teki1-0/+6
Add weak led_setup() so that board which has an uncommon led setup code that can make use of custom implementation. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22rockchip: rk3288: Add OF board setupJagan Teki2-0/+31
The new rk3288 revision rk3288w has some changes with respect to legacy rk3288 like hclk_vio in cru and usb host0 ohci. Linux clock driver already handle this via rockchip,rk3288w-cru compatible. USB ohci host can enable via dts for rk3288w based boards. So, add fdt board setup code to update cru compatible with rk3288w-cru compatible if the SOC revision is RK3288W. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22rockchip: Add rk3288 SoC detection helperJagan Teki1-0/+49
Rockchip SoC's has a new revision chip for rk3288 SoCs. RK3288 has a new revision chip called RK3288W which is similar but different hclk_vio clock and fixed OHCI host. Add common Rockchip SoC detection helper to support this rk3288w detection. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22arm64: dts: rockchip: Add Radxa ROCK Pi 4C supportJagan Teki3-0/+58
Rock PI 4C has AP6256 Wifi/BT, PoE, miniDP, USB Host enabled GPIO pin change compared to 4B, 4C. So, add or enable difference nodes/properties in 4C dts by including common dtsi. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22arm64: dts: rockchip: Add ROCKPi 4A/4B supportJagan Teki5-27/+63
Rock PI 4 has 3 variants of hardware platforms called RockPI 4A, 4B, and 4C. - Rock PI 4A has no Wif/BT. - Rock PI 4B has AP6256 Wifi/BT, PoE. - Rock PI 4C has AP6256 Wifi/BT, PoE, miniDP, USB Host enable GPIO pin change compared to 4B, 4C So move common nodes, properties into dtsi file and include on respective variant dts files. Use 4B dts into default rock-pi-4 defconfig until we find any solution for dynamic detection of these variants. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22rockchip: sdram: fix dram_init_banksizeAlex Bee1-4/+2
Currently 2.5 GB is calculated as DRAM size for a 1 GB RK322x board if CONFIG_SPL_OPTEE is set. This is troublesome when booting a linux kernel since this size will be injected in FDT of the kernel. gd->bd->bi_dram[0].start (which is basically CONFIG_SYS_SDRAM_BASE) must not be taken into consideration for calculation of second bank size, since this offset is already included in calculation of "top". After applying this patch 992 MB (1024 MB - 32 MB reserved for optee-os) is correctly calculated and has also been verified on 2 GB boards. Signed-off-by: Alex Bee <knaerzche@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22rockchip: ram: fix debug funcfion define when RAM_ROCKCHIP_DEBUG not setKever Yang1-15/+0
The empty function define should not be in the header file, or else the build will error with function multi definition after CONFIG_RAM_ROCKCHIP_DEBUG is disabled. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22ARM: dts: rk3328-rock64: Add SPI Flash supportJohannes Krottmayer1-0/+6
Add U-Boot SPI Flash support for the PINE64 Rock64 board Signed-off-by: Johannes Krottmayer <krjdev@gmail.com> Cc: Matwey V. Kornilov <matwey.kornilov@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22ARM: dts: rk3328: Add SPI supportJohannes Krottmayer1-0/+5
Add U-Boot SPI support for the RK3328 Signed-off-by: Johannes Krottmayer <krjdev@gmail.com> Cc: Kever Yang <kever.yang@rock-chips.com> Cc: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> (fix checkpatch error for code ident) Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22rockchip: board: add Hardkernel Odroid Go2 boardHeiko Stuebner2-0/+76
Also known as Odroid Go Advance but named Go2 internally by the vendor it seems. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22rockchip: px30: sync Odroid Go Advance devicetree from LinuxHeiko Stuebner2-1/+718
Get the devicetree from mainline Linux and include it for U-Boot uses. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22rockchip: px30: sync the main rk3326 dtsi from mainlineHeiko Stuebner1-0/+15
The rk3326 is just a trimmed down px30 from a software perspective, so the mainline rk3326 dtsi also ist just a tiny addition. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-20treewide: convert devfdt_get_addr() to dev_read_addr()Masahiro Yamada2-2/+2
When you enable CONFIG_OF_LIVE, you will end up with a lot of conversions. To generate this commit, I used coccinelle excluding drivers/core/, include/dm/, and test/ The semantic patch that makes this change is as follows: <smpl> @@ expression dev; @@ -devfdt_get_addr(dev) +dev_read_addr(dev) </smpl> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-20arm: mach-k3: Use SOC driver for device identificationDave Gerlach3-36/+19
Make use of UCLASS_SOC to find device family and revision for print_cpuinfo. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2020-07-20arm: dts: k3-j721e-mcu-wakeup: Introduce chipid nodeDave Gerlach2-0/+9
Introduce a chipid node to provide a UCLASS_SOC driver to identify TI K3 SoCs. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2020-07-20arm: dts: k3-am65-wakeup: Introduce chipid nodeDave Gerlach2-0/+9
Introduce a chipid node to provide a UCLASS_SOC driver to identify TI K3 SoCs. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2020-07-20test: Add tests for SOC uclassDave Gerlach1-0/+4
Add a sandbox SOC driver, and some tests for the SOC uclass. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2020-07-20cpu: Convert the methods to use a const udevice *Simon Glass8-18/+21
These functions should not modify the device. Convert them to const so that callers don't need to cast if they have a const udevice *. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-07-20x86: mp: Add more comments to the moduleSimon Glass2-3/+102
Add a description of how this module works and also some missing function comments. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-20x86: mtrr: Add support for writing to MTRRs on any CPUSimon Glass2-0/+102
To enable support for the 'mtrr' command, add a way to perform MTRR operations on selected CPUs. This works by setting up a little 'operation' structure and sending it around the CPUs for action. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-07-20x86: mtrr: Update MTRRs on all CPUsSimon Glass1-0/+57
When the boot CPU MTRRs are updated, perform the same update on all other CPUs so they are kept in sync. This avoids kernel warnings about mismatched MTRRs. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-20x86: Don't enable SMP in SPLSimon Glass2-2/+2
SMP should be set up in U-Boot where possible, not SPL. Disable it in SPL. For 64-bit U-Boot we should find a way to allow SMP operations in U-Boot, but this is somewhat more complicated. For now that is disabled too. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-07-20x86: mtrr: Use MP calls to list the MTRRsSimon Glass2-0/+41
Update the mtrr command to use mp_run_on_cpus() to obtain its information. Since the selected CPU is the boot CPU this does not change the result, but it sets the stage for supporting other CPUs. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-20x86: mp: Add iterators for CPUsSimon Glass2-0/+105
It is convenient to iterate through the CPUs performing work on each one and processing the result. Add a few iterator functions which handle this. These can be used by any client code. It can call mp_run_on_cpus() on each CPU that is returned, handling them one at a time. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-20x86: mp: Park CPUs before running the OSSimon Glass3-0/+38
With the new MP features the CPUs are no-longer parked when the OS is run. Fix this by calling a special function to park them, just before the OS is started. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-20x86: mp: Allow running functions on multiple CPUsSimon Glass2-6/+134
Add a way to run a function on a selection of CPUs. This supports either a single CPU, all CPUs, just the main CPU or just the 'APs', in Intel terminology. It works by writing into a mailbox and then waiting for the CPUs to notice it, take action and indicate they are done. When SMP is not yet enabled, this just calls the function on the main CPU. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-20x86: Set the SMP flag when MP init is completeSimon Glass1-0/+1
Set this flag so we can track when it is safe to use CPUs other than the main one. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
generated by cgit v1.2.3 (git 2.39.0) at 2024-10-07 06:09:40 +0300