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2022-10-11Merge tag 'xilinx-for-v2023.01-rc1-v3' of ↵Tom Rini9-13/+15
https://source.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2023.01-rc1 (round 3) fpga: - Create new uclass - Get rid of FPGA_DEBUG and use logging infrastructure zynq: - Enable early EEPROM decoding - Some DT updates zynqmp: - Use OCM_BANK_0 to check config loading permission - Change config object loading in SPL - Some DT updates net: - emaclite: Enable driver for RISC-V xilinx: - Fix static checker warnings - Fix GCC12 warning sdhci: - Read PD id from DT
2022-10-09imx: gpmi: Add register needed to control nand bus timingMichael Trimarchi1-0/+9
It is used as delay for gpmi write strobe. Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Reviewed-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2022-10-07Merge branch '2022-10-07-riscv-toolchain-update'Tom Rini1-1/+10
- Update RISC-V to use 32bit or 64bit toolchains, depending on if we're building for 32bit or 64bit CPUs. This requires updating the Docker container as well to have the 32bit toolchain.
2022-10-07riscv: Fix build against binutils 2.38Alexandre Ghiti1-1/+10
The following description is copied from the equivalent patch for the Linux Kernel proposed by Aurelien Jarno: >From version 2.38, binutils default to ISA spec version 20191213. This means that the csr read/write (csrr*/csrw*) instructions and fence.i instruction has separated from the `I` extension, become two standalone extensions: Zicsr and Zifencei. As the kernel uses those instruction, this causes the following build failure: arch/riscv/cpu/mtrap.S: Assembler messages: arch/riscv/cpu/mtrap.S:65: Error: unrecognized opcode `csrr a0,scause' arch/riscv/cpu/mtrap.S:66: Error: unrecognized opcode `csrr a1,sepc' arch/riscv/cpu/mtrap.S:67: Error: unrecognized opcode `csrr a2,stval' arch/riscv/cpu/mtrap.S:70: Error: unrecognized opcode `csrw sepc,a0' Signed-off-by: Alexandre Ghiti <alexandre.ghiti@canonical.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Tested-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Christian Stewart <christian@paral.in> Reviewed-by: Rick Chen <rick@andestech.com>
2022-10-07arm64: zynqmp: Fix compiler warnings in mp.cVenkatesh Yadav Abbarapu1-3/+3
make W=1 generates the following warning in cpu_disable, cpu_status and cpu_release functions. arch/arm/mach-zynqmp/mp.c:166:16: warning: comparison of unsigned expression in '>= 0' is always true [-Wtype-limits] 166 | if (nr >= ZYNQMP_CORE_APU0 && nr <= ZYNQMP_CORE_APU3) { | ^~ Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> Link: https://lore.kernel.org/r/20221004053454.25470-1-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-10-07arm: nuvoton: Add support for Nuvoton NPCM845 BMCJim Liu13-0/+780
Add basic support for the Nuvoton NPCM845 EVB (Arbel). Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2022-10-07armv8: cache_v8: Fix pgtables setup when MMU is already enabledPali Rohár1-0/+4
When MMU is already enabled then dcache_enable() does not call mmu_setup() and so setup_all_pgtables() is also never called. In this situation when some driver calls mmu_set_region_dcache_behaviour() function then U-Boot crashes with error message: Emergency page table not setup. Fix this issue by explicitly calling setup_all_pgtables() in dcache_enable() function near condition for mmu_setup(). This change fixes chainloading U-Boot from U-Boot on Turris Mox board which uses mvneta ethernet driver which calls mmu_set_region_dcache_behaviour(). Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <kabel@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2022-10-07common/board_f: introduce arch_setup_dest_addr()Ovidiu Panait1-0/+17
In order to move ppc-specific code out of setup_dest_addr(), provide an arch-specific variant arch_setup_dest_addr(), that can be used by architecture code to fix up the initial reloc address. It is called at the end of setup_dest_addr() initcall and the default implementation is a nop stub. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
2022-10-07common/board_f: move CONFIG_MACH_TYPE logic to arch/arm/lib/bdinfo.cOvidiu Panait1-0/+12
asm/mach_type.h header and CONFIG_MACH_TYPE macro are arm-specific, so move related bdinfo logic to arch_setup_bdinfo() in arch/arm/lib/bdinfo.c. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
2022-10-07common/board_f: remove XTRN_DECLARE_GLOBAL_DATA_PTR dead codeOvidiu Panait1-6/+0
The XTRN_DECLARE_GLOBAL_DATA_PTR declarations in ppc code are permanently commented out, so there are no users for this macro: #if 1 #define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r2") #else /* We could use plain global data, but the resulting code is bigger */ #define XTRN_DECLARE_GLOBAL_DATA_PTR extern #define DECLARE_GLOBAL_DATA_PTR XTRN_DECLARE_GLOBAL_DATA_PTR \ gd_t *gd #endif Remove all references to this macro, but add a documentation note regarding the possibility of using plain global data for the GD pointer. Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2022-10-06arm: mvebu: Add support for specifying VHV_Enable GPIOPali Rohár2-3/+54
VHV_Enable GPIO is required to enable during eFuse programming on Armada SoCs not from 3700 family. Add support for enabling and disabling VHV pin via GPIO during eFuse programming, when specified. All details are in Marvell AN-389: ARMADA VHV Power document (Doc. No. MV-S302545-00 Rev. C, August 2, 2016). Note that due to HW Errata 3.6 eFuse erroneous burning (Ref #: HWE-3718342) VHV power must be disabled while core voltage is off to prevent erroneous eFuse programming. This is specified in Marvell ARMADA 380/385/388 Functional Errata, Guidelines, and Restrictions document (Doc. No. MV-S501377-00 Rev. D, December 1, 2016). Signed-off-by: Pali Rohár <pali@kernel.org>
2022-10-06arm: mvebu: Add support for programming LD0 and LD1 eFusePali Rohár2-0/+47
This patch implements LD eFuse programming support. Armada 385 contains two LD eFuse lines, each is 256 bit long with one additional lock bit. LD 0 line is mapped to U-Boot fuse bank 64 and LD 1 line to fuse bank 65. U-Boot 32-bit fuse words 0-8 are mapped to LD eFuse line bits 0-255. U-Boot fuse word 9 is mapped to LD eFuse line lock bit. So to program LD 1 General Purpose Data line, use U-Boot fuse command: => fuse prog -y 65 0 0x76543210 => fuse prog -y 65 1 0xfedcba98 => fuse prog -y 65 2 0x76543210 => fuse prog -y 65 3 0xfedcba98 => fuse prog -y 65 4 0x76543210 => fuse prog -y 65 5 0xfedcba98 => fuse prog -y 65 6 0x76543210 => fuse prog -y 65 7 0xfedcba98 => fuse prog -y 65 8 0x1 Signed-off-by: Pali Rohár <pali@kernel.org>
2022-10-06arm: mvebu: Remove timer.cStefan Roese3-48/+0
Since the move to CONFIG_TIMER with support for CONFIG_TIMER_EARLY, this platform specific init_timer() function is not needed any more. Let's remove it completely. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Michael Walle <michael@walle.cc> Cc: Pali Rohár <pali@kernel.org>
2022-10-06board/km: remove kirkwood boardsHolger Brunck3-102/+0
These boards are out of maintenance and can be removed. Signed-off-by: Holger Brunck <holger.brunck@hitachienergy.com> Reviewed-by: Stefan Roese <sr@denx.de>
2022-10-05arm64: dts: Remove unused property device_idAshok Reddy Soma5-6/+0
Device tree property "xlnx,device_id" is not used anymore, remove it. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Link: https://lore.kernel.org/r/20220930092548.18453-4-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-10-05ARM: zynq: Define rtc alias on zc702/zc706Michal Simek2-2/+4
Define rtc alias on zc702/zc706 boards. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/47df614929d49af9f562c103defb92900de9d3e1.1664279424.git.michal.simek@amd.com
2022-10-05ARM: zynq: Point via nvmem0 alias to eeprom on zc702/zc706Michal Simek2-2/+4
EEPROM stores identification information about board like a board name, revision, serial number and ethernet MAC address. U-Boot is capable to read nvmemX aliases and read/display provided information when nvmem alias link is described. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/c63bba87d0400b6bd0f5651fac21d525f12288f5.1664265311.git.michal.simek@amd.com
2022-10-05dm: fpga: Introduce new uclassAlexander Dahl1-0/+4
For future DM based FPGA drivers and for now to have a meaningful logging class for old FPGA drivers. Suggested-by: Michal Simek <michal.simek@amd.com> Suggested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Alexander Dahl <post@lespocky.de> Reviewed-by: Simon Glass <sjg@chromium.org> Link: https://lore.kernel.org/r/20220930120430.42307-2-post@lespocky.de Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-10-03Merge branch 'next'Tom Rini219-2315/+4695
2022-10-03imx8mn-ddr4-evk-u-boot: Fix broken bootFabio Estevam1-0/+4
When the imx8mn.dtsi file was pulled in from Linux, the UARTs were moved into an spba sub-node which wasn't being included in the SPL device tree. This meant the references to the UART weren't being handled properly and when booting the system would constantly reboot. Fix this by adding the spba node to the spl device tree to restore normal booting. Based on the patch from Adam Ford for the imx8mn-beacon-kit-u-boot board. Fixes: 4e5114daf9eb ("imx8mn: synchronise device tree with linux") Signed-off-by: Fabio Estevam <festevam@denx.de>
2022-10-03imx8mn-venice-u-boot: Fix broken bootFabio Estevam1-0/+4
When the imx8mn.dtsi file was pulled in from Linux, the UARTs were moved into an spba sub-node which wasn't being included in the SPL device tree. This meant the references to the UART weren't being handled properly and when booting the system would constantly reboot. Fix this by adding the spba node to the spl device tree to restore normal booting. Based on the patch from Adam Ford for the imx8mn-beacon-kit-u-boot board. Fixes: 4e5114daf9eb ("imx8mn: synchronise device tree with linux") Signed-off-by: Fabio Estevam <festevam@denx.de>
2022-09-29dm: core: Drop ofnode_is_available()Simon Glass3-3/+3
This function is also available as ofnode_is_enabled(), so use that instead. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-29sandbox: Support setting up the other FDT for testingSimon Glass2-3/+50
Provide a way to copy over the 'other' FDT when running tests. This loads it and allocates memory for the copy, if not done already, then does the copy. Avoid using U-Boot's malloc() pool for these copies, at least for now, since they are part of the test system. Tidy up the cpu.c header files while here. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-29sandbox: Support loading the other FDTSimon Glass4-1/+78
We need an 'other' FDT which is different from the control FDT, so we can check that the ofnode tests correctly handle them both. Add this to the build along with a way to read it into the sandbox state. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-29sandbox: Add a function to load a relative file pathSimon Glass3-9/+43
At present this implementation is specific to loading the test FDT. We plan to load others, so create a generic function to handle this. The path is now limited to 256 characters, to simplify the code. When there is an empty argv[0] (which should not happen), the function now just uses the path as is, with no prefix. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-29test: Support testing malloc() failuresSimon Glass1-0/+1
It is helpful to test that out-of-memory checks work correctly in code that calls malloc(). Add a simple way to force failure after a given number of malloc() calls. Fix a header guard to avoid a build error on sandbox_vpl. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Sean Anderson <seanga2@gmail.com>
2022-09-29treewide: Drop image_header_t typedefSimon Glass10-22/+22
This is not needed and we should avoid typedefs. Use the struct instead and rename it to indicate that it really is a legacy struct. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-29treewide: Drop bootm_headers_t typedefSimon Glass14-43/+44
This is not needed and we should avoid typedefs. Use the struct instead. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-27Merge tag 'u-boot-stm32-20220927' of ↵Tom Rini36-455/+634
https://source.denx.de/u-boot/custodians/u-boot-stm into next - Increase SYS_MALLOC_F_LEN for STM32 MCU's board - SPL fixes for STM32F7 MCUs - Device tree alignement with kernelv6.0-rc4 for MCU's board - Device tree alignement with kernelv6.0-rc3 for MPU's board - Update DDR node for STM32MP15 - Cleanup config file for STM32MP1 - Update for cmd_stm32key command - Fix compatible string to add partitions for STM32MP1 - Update for stm32programmer tool
2022-09-26Merge tag 'xilinx-for-v2023.01-rc1-v2' of ↵Tom Rini17-38/+398
https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next Xilinx changes for v2023.01-rc1 (round 2) xilinx: - Add support for new Versal NET SOC zynqmp: - Use mdio bus for ethernet phy description - Wire ethernet phy reset via i2c-gpio versal: - Config cleanup
2022-09-26Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-riscv ↵Tom Rini10-11/+163
into next
2022-09-26configs: stm32f769-disco: Fix internal flash sizePatrice Chotard1-3/+3
arch-stm32f7/stm32.h file is shared between STM32F746 and STM32F769 MCUs. But STM32F769 embeds 2MB of internal flash instead of 1MB for STM32F746. The flash layout is quite similar between the 2 SoCs : STM32F746 STM32F769 4 * 32KB sectors 4 * 32KB sectors 1 * 128KB sector 1 * 128KB sector 3 * 256KB sectors 7 * 256KB sectors Update sect_sz_kb[] structure and SYS_MAX_FLASH_SECT accordingly. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Tested-by: Waldemar Brodkorb <wbx@openadk.org>
2022-09-26ARM: dts: stm32: DT sync with kernel v6.0-rc4 for MCU's boardsPatrice Chotard19-275/+209
Device tree alignment with kernel v6.0-rc4. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-09-26arm64: versal-net: Add support for mini configurationMichal Simek2-0/+68
Versal NET mini configuration is designed for running memory test. Current output is on DCC but changing serial0 alias to pl011 will move console to serial port. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/aec3f41a4cc48c45b8f07dd6e423d5838dbcc9d7.1663589964.git.michal.simek@amd.com
2022-09-26spi: cadence_qspi: Add support for Versal NET platformMichal Simek1-0/+4
Trivial changes to support cadence ospi driver for Versal NET platform. Also avoid ospi flash reset for now. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/0789141f432189aab69bc496fe33e0218d1d7510.1663589964.git.michal.simek@amd.com
2022-09-26arm64: versal-net: Add support for Versal NET platformMichal Simek10-0/+248
Versal NET platform is based on Versal chip which is reusing a lot of IPs. For more information about new IPs please take a look at DT which describe currently supported devices. The patch is adding architecture and board support with soc detection algorithm. Generic setting should be very similar to Versal but it will likely diverge in longer run. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/320206853dc370ce290a4e7b6d0bb26b05206021.1663589964.git.michal.simek@amd.com
2022-09-26riscv: Introduce AVAILABLE_HARTSRick Chen6-5/+23
In SMP all harts will register themself in available_hart during start up. Then main hart will send IPI to other harts according to this variables. But this mechanism may not guarantee that all other harts can jump to next stage. When main hart is sending IPI to other hart according to available_harts, but other harts maybe still not finish the registration. Then the SMP booting will miss some harts finally. So let it become an option and it will be enabled by default. Please refer to the discussion: https://www.mail-archive.com/u-boot@lists.denx.de/msg449997.html Signed-off-by: Rick Chen <rick@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2022-09-26spl: introduce SPL_XIP to configNikita Shubin6-6/+13
U-Boot and SPL don't necessary share the same location, so we might end with U-Boot SPL in read-only memory (XIP) and U-Boot in read-write memory. In case of non XIP boot mode, we rely on such variables as "hart_lottery" and "available_harts_lock" which we use as atomics. The problem is that CONFIG_XIP also propagate to main U-Boot, not only SPL, so we need CONFIG_SPL_XIP to distinguish SPL XIP from other XIP modes. This adds an option special for SPL to behave it in XIP manner and we don't use hart_lottery and available_harts_lock, during start proccess. Signed-off-by: Nikita Shubin <n.shubin@yadro.com> Reviewed-by: Rick Chen <rick@andestech.com>
2022-09-25sandbox: Add a test for SCSISimon Glass2-0/+9
Add a simple uclass test for SCSI. It reads the partition table from a disk image and checks that it looks correct. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-25sandbox: Convert to use driver model for SCSISimon Glass1-1/+0
At present sandbox is producing a warning about SCSI migration. Drop the legacy code and replace it with a new implementation. Also drop the SATA command, which does not work with driver model. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-25sandbox: unblock signal before calling execv()Heinrich Schuchardt1-0/+16
The following faulty behavior was observed. The sandbox configured with CONFIG_SANDBOX_CRASH_RESET=y was invoked with ./u-boot -T -S After executing `exception undefined' the sandbox reboots. When executing `exception undefined' the sandbox exits with SIGSEGV. The expected behavior is that the sandbox should reboot again. If we are relaunching the sandbox in a signal handler, we have to unblock the respective signal before calling execv(). See signal(7) man-page. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-09-24sandbox: Add function os_flush()Pali Rohár1-0/+5
It flushes stdout. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-09-23powerpc/mpc85xx: Fix re-align of unmapped DDR memory message for non-SPL buildsPali Rohár1-0/+3
During init_dram() is called also setup_ddr_tlbs_phys() function which may print message about unmapped DDR memory. So in this case print also re-aligning filler after unmapped DDR memory message. Signed-off-by: Pali Rohár <pali@kernel.org>
2022-09-23powerpc/mpc85xx: Explain TLB unmapped memory messagePali Rohár1-1/+1
Currently U-Boot SPL prints just generic message "2 GiB left unmapped". Change it to more detailed "2 GiB of DDR memory left unmapped in U-Boot". This is just U-Boot configuration and operating system may map more (or also less) memory. Signed-off-by: Pali Rohár <pali@kernel.org>
2022-09-23board_f: Fix types for board_get_usable_ram_top()Pali Rohár25-26/+26
Commit 37dc958947ed ("global_data.h: Change ram_top type to phys_addr_t") changed type of ram_top member from ulong to phys_addr_t but did not changed types in board_get_usable_ram_top() function which returns value for ram_top. So change ulong to phys_addr_t type also in board_get_usable_ram_top() signature and implementations. Fixes: 37dc958947ed ("global_data.h: Change ram_top type to phys_addr_t") Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-09-23arm: dts: mt7622: add i2c supportWeijie Gao2-0/+42
Add both hardware and software i2c support for mt7622. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2022-09-23arm: dts: mt7622: force high-speed mode for uartWeijie Gao1-0/+1
The input clock for uart is too slow (25MHz) which introduces frequent data error on both receiving and transmitting even if the baudrate is 115200. Using high-speed can significantly solve this issue. Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Daniel Golle <daniel@makrotopia.org> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2022-09-23board: mediatek: add MT7981 reference boardsWeijie Gao4-0/+454
This patch adds general board files based on MT7981 SoCs. MT7981 uses one mmc controller for booting from both SD and eMMC, and the pins of mmc controller are also shared with spi controller. So three configs are need for these boot types: 1. mt7981_rfb_defconfig - SPI-NOR and SPI-NAND 2. mt7981_emmc_rfb_defconfig - eMMC only 3. mt7981_sd_rfb_defconfig - SD only Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2022-09-23board: mediatek: add MT7986 reference boardsWeijie Gao7-0/+810
Add general board files based on MT7986 SoCs. MT7986 uses one mmc controller for booting from both SD and eMMC. Both MT7986A and MT7986B use the same pins for spi controller. Configs for various boot types: 1. mt7986_rfb_defconfig - SPI-NOR and SPI-NAND for MT7986A/B 2. mt7986a_bpir3_emmc_defconfig - eMMC for MT7986A only 3. mt7986a_bpir3_sd_defconfig - SD for MT7986A only Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2022-09-23arm: mediatek: add support for MediaTek MT7981 SoCWeijie Gao6-1/+389
This patch adds basic support for MediaTek MT7981 SoC. This include the file that will initialize the SoC after boot and its device tree. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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