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2021-10-18board: arm: Remove OF_PRIOR_STAGE from the remaining Arm boardsIlias Apalodimas1-1/+0
At some point back in 2018 prior_stage_fdt_address and OF_PRIOR_STAGE got introduced, in order to support a DTB handed over by an earlier stage boo loader. However we have another option in the Kconfig (OF_BOARD) which has identical semantics. So let's remove the option in an effort to simplify U-Boot's config and DTB management, and use OF_BOARD instead. Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-10-18riscv: Remove OF_PRIOR_STAGE from RISC-V boardsIlias Apalodimas3-11/+3
At some point back in 2018 prior_stage_fdt_address and OF_PRIOR_STAGE got introduced, in order to support a DTB handed over by an earlier stage boo loader. However we have another option in the Kconfig (OF_BOARD) which has identical semantics. On RISC-V some of the boards pick up the DTB from a1 and copy it in their private gd_t. Apart from that they copy it to prior_stage_fdt_address, if the Kconfig option is selected, which is unnecessary. So let's switch the config option for those boards to OF_BOARD and define the required board_fdt_blob_setup() for them. Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-10-18Merge tag 'u-boot-rockchip-20211015' of ↵Tom Rini4-8/+18
https://source.denx.de/u-boot/custodians/u-boot-rockchip - Fix for Rockchip mmc HS400 mode; - Fix for px30 board Odroid Go; - rockchip_sfc update; - rk3568 clk update; - doc fix;
2021-10-16Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-tegraTom Rini4-2/+160
On merge, fixup order of fdtdec_add_reserved_memory parameters in arch/arm/cpu/armv8/fsl-layerscape/soc.c Signed-off-by: Tom Rini <trini@konsulko.com>
2021-10-15Convert CONFIG_USB_EHCI_IS_TDI to KconfigMarek Behún2-7/+1
On mvebu this is defined if and only if !ARM64. Otherwise it is defined for boards with ARCH_MX23, ARCH_TEGRA and ARCH_ZYNQ, and also for SOC_AR934X (tplink_wdr4300). Signed-off-by: Marek Behún <marek.behun@nic.cz>
2021-10-15Rename CONFIG_EHCI_IS_TDI to CONFIG_USB_EHCI_IS_TDIMarek Behún1-1/+1
In preparation for moving this option to Kconfig, rename it to be consistent with other USB EHCI Kconfig options. Signed-off-by: Marek Behún <marek.behun@nic.cz>
2021-10-15clk: rockchip: rk3568: update clksElaine Zhang1-1/+1
fix up ppll init freq. support tclk_emmc. add freq (26M) for mmc device. fix up the sfc clk rate unit error. Change in V2: remove change id. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-10-15rockchip: px30: sync serial flash controller bindings with mainlineChris Morgan3-7/+7
The devicetree submitted and approved for the mainline linux kernel is slightly different than the one present here. This syncs both devicetrees (for the Rockchip SFC node at least) present on the PX30 and the Odroid Go Advance. Changes include renaming the flash node, reordering the values in the SFC node for the rk3326-odroid-go2, changing the name of the cs pinctrl node to cs0, and updating the u-boot specific tree to utilize the new flash node value. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-10-15rockchip: board: remove SCLK_GPU from U-Boot DTChris Morgan1-0/+10
Starting with commit 92f1e9a4b31c ("clk: Detect failure to set defaults") the clk driver for the PX30 would fail to probe for the Odroid Go Advance. This patch is to remove the clock for the GPU from the U-Boot specific devicetree, as that clock is not supported by the U-Boot clk_px30 driver. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-10-15scripts: remove some configs in config_whitelist.txtPatrick Delaunay1-4/+4
Remove some config finishing by _ badly added by scripts/build-whitelist.sh when joker is used in comments. for example: doc/uImage.FIT/command_syntax_extensions.txt: ... #ifdef CONFIG_OF_* | ... cmd/nvedit.c:# error Define one of CONFIG_ENV_IS_IN_{EEPROM| \ FLASH|MMC|FAT|EXT4|\ Remove also configs only used in comments: - CONFIG_BOOGER in include/linux/kconfig.h - CONFIG_COMMANDS - CONFIG_INIT_IGNORE_ERROR - CONFIG_REG_* - CONFIG_HOTPLUG : drivers/watchdog/omap_wdt.c:18 Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2021-10-14ARM: tegra: Copy memory-region-names propertyThierry Reding1-1/+30
If multiple entries are present in the memory-region property, this new memory-region-names property can be used to specify names for each of them so that they can be more easily distinguished. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2021-10-14ARM: tegra: Refactor DT update helpersThierry Reding2-0/+128
Rather than duplicate the Ethernet MAC address and carveout updating code for each board, move it to a common location and make it more reusable. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2021-10-14fdtdec: Support reserved-memory flagsThierry Reding2-2/+2
Reserved memory nodes can have additional flags. Support reading and writing these flags to ensure that reserved memory nodes can be properly parsed and emitted. This converts support for the existing "no-map" flag to avoid extending the argument list for fdtdec_add_reserved_memory() to excessive length. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2021-10-14fdtdec: Support compatible string list for reserved memoryThierry Reding2-2/+3
Reserved memory nodes can have a compatible string list to identify the type of reserved memory that they represent. Support specifying an optional compatible string list when creating these nodes. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2021-10-12Merge tag 'u-boot-stm32-20211012' of ↵Tom Rini4-5/+13
https://source.denx.de/u-boot/custodians/u-boot-stm - Disable ATAGS for STM32 MCU and MPU boards - Disable bi_boot_params for STM32 MCU and MPU boards - Update stm32-usbphyc node management - Convert CONFIG_STM32_FLASH to Kconfig for STM32 MCU boards - Convert some USB config flags to Kconfig for various boards - Convert CONFIG_BOOTCOMMAND flag to Kconfig for STM32 F429 board - Remove specific CONFIG_STV0991 flags - Remove unused CONFIG_USER_LOWLEVEL_INIT flag - Add ofdata_to_platdata() callback for stm32_spi driver - Update for stm32f7_i2c driver - Remove gpio_hog_probe_all() from STM32 MP1 board - Fix bind command Signed-off-by: Tom Rini <trini@konsulko.com>
2021-10-12Merge tag 'u-boot-at91-2022.01-b' of ↵Tom Rini1-0/+8
https://source.denx.de/u-boot/custodians/u-boot-at91 Second set of u-boot-at91 features for the 2022.01 cycle: This small feature set adds the support for PWM driver for the sama5d2 SoC. It also adds a node in the DT for this SoC.
2021-10-12Merge https://source.denx.de/u-boot/custodians/u-boot-sunxiTom Rini13-526/+278
The bulk of it is Samuel's DM_I2C rework, which removes the nasty I2C deprecation warnings for most 32-bit boards. It also includes some smaller refactorings that pave the way for more changes, mostly driven by needing to support the Allwinner RISC-V SoC later on. Board wise we gain support for the FriendlyARM NanoPi R1S H5 router board and official Pinetab support. Build-tested for all 160 sunxi boards, and boot tested on a A64, A20, H3, H6, and H616 board. USB, SD card, eMMC, and Ethernet all work there (where applicable).
2021-10-12ARM: dts: sama5d2: Add pwm0 definitionDan Sneddon1-0/+8
Add node for the PWM0 on the SAMA5D2 SoC. Signed-off-by: Dan Sneddon <dan.sneddon@microchip.com>
2021-10-12sunxi: Enable DM_I2C for all sunxi boardsSamuel Holland2-3/+1
Now that the last users of legacy I2C (outside of SPL) have been resolved, we can enable DM_I2C at the sunxi architecture level. Reviewed-by: Heiko Schocher <hs@denx.de> Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-12sunxi: video: Convert panel I2C to use DM_I2CSamuel Holland1-15/+6
Two displays supported by the sunxi display driver (each one used by a single board) require initialization over I2C. Both previously used i2c_soft; replace this with the i2c-gpio instance that already exists in those boards' device trees (sun5i-a13-utoo-p66 and sun6i-a31-colombus). Since the i2c-gpio nodes are not referenced by any other node in the device trees (the device trees have no panel node), the I2C bus is selected by its node name. This panel initialization code was the only i2c_soft user, so the i2c_soft GPIO setup code can be removed now as well. Reviewed-by: Heiko Schocher <hs@denx.de> Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-12sunxi: pmic_bus: Use the DM PMIC interface when possibleSamuel Holland2-0/+21
The pmic_bus functions are used in both SPL (for regulator setup) and U-Boot proper (for regulator setup, SID access, GPIO, and poweroff). Currently, pmic_bus conflicts with DM_I2C because it uses the legacy I2C interface. This commit makes pmic_bus dual-compatible with either the legacy I2C functions or the newly-added PMIC_AXP driver (which uses DM_I2C). In turn, this allows platforms to start transitioning to DM_I2C in U-Boot proper, without breaking boards that still depend on the legacy I2C interface for other reasons. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-12sunxi: pmic_bus: Clean up preprocessor conditionsSamuel Holland1-51/+39
Instead of using the SoC symbols to decide the bus type, use whichever bus driver is actually enabled. This allows collapsing all of the AXP2xx and AXP8xx variants into one "else" case. It also has the advantage of falling back to I2C when the other bus drivers are disabled; this works because all of the PMICs support I2C in addition to other interfaces. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-12i2c: Add a DM_I2C driver for the sun8i RSB controllerSamuel Holland4-194/+11
This bus controller is used to communicate with an X-Powers AXP PMIC. Currently, various drivers access PMIC registers through a platform- specific non-DM "pmic_bus" interface, which depends on the legacy I2C framework. In order to convert those drivers to use DM_PMIC, this bus needs a DM_I2C driver. Refactor the rsb functions to take the base address as a parameter, and implement both the existing interface (which is still needed in SPL) and the DM_I2C interface on top of them. The register for switching between I2C/P2WI/RSB mode is the same across all PMIC variants, so move that to the common header. There are only a couple of pairs of hardware/runtime addresses used across all PMIC variants. So far the code expected only the "primary" pair, but some PMICs like the AXP305 and AXP805 use the secondary pair, so add support for that to the DM driver as well. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-12i2c: Add a DM_I2C driver for the sun6i P2WI controllerSamuel Holland4-134/+5
This bus controller is used to communicate with an X-Powers AXP PMIC. Currently, various drivers access PMIC registers through a platform- specific non-DM "pmic_bus" interface, which depends on the legacy I2C framework. In order to convert those drivers to use DM_PMIC, this bus needs a DM_I2C driver. Refactor the p2wi functions to take the base address as a parameter, and implement both the existing interface (which is still needed in SPL) and the DM_I2C interface on top of them. The register for switching between I2C/P2WI/RSB mode is the same across all PMIC variants. Move that to the common header, so it can be used by both interface implementations. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-12sunxi: pmic_bus: Fix Kconfig dependenciesSamuel Holland1-1/+2
AXP_PMIC_BUS enables communication with a specific AXP PMIC at a PMIC-dependent I2C/P2WI/RSB bus address. It is automatically selected as a dependency of the PMIC driver. It should not be selectable by the user when no PMIC is chosen. AXP_GPIO uses the pmic_bus functions, and also depends on a specific PMIC header to pick up register definitions. Both of these changes have no impact on any existing configs, since the code does not compile if the dependencies are not met. Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-12sunxi: Select SUN8I_RSB more carefullySamuel Holland1-2/+3
SUN8I_RSB should not be selected by MACH_SUN8I, because the hardware is not present in half of those SoCs (H3/H5, R40, and V3s). Move the selection to the SoCs where the hardware actually exists. As it currently stands, selecting that option also requires using it in some way, which is not the case for one A80 board. Since we have only three A80 boards in total, we select it their via their defconfigs. Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Samuel Holland <samuel@sholland.org> [Andre: fixing up Sunchip_CX-A99 build] Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-12sunxi: Only initialize legacy I2C when enabledSamuel Holland1-1/+1
CONFIG_SPL_I2C is the wrong symbol to use here. It is the top-level Kconfig symbol (not specific to either legacy or DM I2C), whereas the i2c_init() function is specific to legacy I2C. This change fixes a build failure when enabling SPL_I2C but not SPL_SYS_I2C_LEGACY. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-by: Andre Przywara <andre.przywara@arm.com>
2021-10-11arm: dts: Update IOT2050 device tree filesJan Kiszka2-1/+30
This fixes the usage of the USB 3.0-capable port under U-Boot as USB 2.0-only port. Original patch by Chao Zeng. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
2021-10-11board: siemens: iot2050: Adjust to changes in DT and configurationJan Kiszka1-1/+1
Account for the changes done between merge proposal and the final merge. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2021-10-11clk: ti: add am33xx/am43xx spread spectrum clock supportDario Binacchi1-0/+12
The patch enables spread spectrum clocking (SSC) for MPU and LCD PLLs. As reported by the TI spruh73x/spruhl7x RM, SSC is only supported for the DISP/LCD and MPU PLLs on am33xx/am43xx. SSC is not supported for DDR, PER, and CORE PLLs. Calculating the required values and setting the registers accordingly was taken from the set_mpu_spreadspectrum routine contained in the arch/arm/mach-omap2/am33xx/clock_am33xx.c file of the u-boot project. In locked condition, DPLL output clock = CLKINP *[M/N]. In case of SSC enabled, the reference manual explains that there is a restriction of range of M values. Since the clk_ti_am3_dpll_round_rate() attempts to select the minimum possible N, the value of M obtained is not guaranteed to be within the range required. With the new "ti,min-div" parameter it is possible to increase N and consequently M to satisfy the constraint imposed by SSC. Link: https://lore.kernel.org/r/20210606202253.31649-6-dariobin@libero.it Signed-off-by: Dario Binacchi <dariobin@libero.it>
2021-10-11ARM: dts: am43xx-clocks: add spread spectrum supportDario Binacchi1-6/+6
Registers for adjusting the spread spectrum clocking (SSC) have been added. As reported by the TI spruhl7x RM, SSC is supported only for LCD and MPU PLLs, but the PRCM_CM_SSC_DELTAMSTEP_DPLL_XXX and PRCM_CM_SSC_MODFREQDIV_DPLL_XXX registers, as well as the enable field in the PRCM_CM_CLKMODE_DPLL_XXX registers are mapped for all PLLs (CORE, MPU, DDR, PER, DISP, EXTDEV). Link: https://lore.kernel.org/r/20210606202253.31649-5-dariobin@libero.it Signed-off-by: Dario Binacchi <dariobin@libero.it>
2021-10-11ARM: dts: am33xx-clocks: add spread spectrum supportDario Binacchi1-5/+5
Registers for adjusting the spread spectrum clocking (SSC) have been added. As reported by the TI spruh73x RM, SSC is supported only for LCD and MPU PLLs, but the CM_SSC_DELTAMSTEP_DPLL_XXX and CM_SSC_MODFREQDIV_DPLL_XXX registers, as well as the enable field in the CM_CLKMODE_DPLL_XXX registers are mapped for all PLLs (CORE, MPU, DDR, PER, DISP). Link: https://lore.kernel.org/r/20210606202253.31649-4-dariobin@libero.it Signed-off-by: Dario Binacchi <dariobin@libero.it>
2021-10-11sunxi: Add support for FriendlyARM NanoPi R1S H5Chukun Pan2-0/+196
This adds support for the NanoPi R1S H5 board. Allwinner H5 SoC 512MB DDR3 RAM 10/100/1000M Ethernet x 2 RTL8189ETV WiFi 802.11b/g/n USB 2.0 host port (A) MicroSD Slot Reset button Serial Debug Port WAN - LAN - SYS LED The dts file is taken from Linux 5.14 tag. Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-11sunxi: gpio: Remove bank-specific size macrosSamuel Holland1-12/+2
Since the beginning, all banks have had space for 32 pins, even when not all pins were implemented. Let's use a single constant for the GPIO bank size here, like the GPIO driver is already doing. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-11sunxi: gpio: Remove name_to_gpio macroSamuel Holland1-1/+0
This clarifies which callers must be updated to complete the DM_GPIO conversion. The only remaining caller of name_to_gpio in generic code is inside the !DM_GPIO block in cmd/gpio.c. DM_GPIO is always selected on sunxi, so that code cannot be reached. And after this commit, there are only two remaining implementations of name_to_gpio. Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-11sunxi: Clean up inclusions of asm/arch/gpio.hSamuel Holland3-3/+0
As part of migrating to DM_GPIO and DM_PINCTRL, eventually we will remove the asm/arch/gpio.h header. In preparation, clean up the various files that include it. Some files did not contain any GPIO code at all, so this header was completely unused. A few files contained only legacy platform-specific GPIO code for setting up pin muxes. They were left unchanged, as that code will be completely removed by the DM_PINCTRL migration. The remaining files contain some combination of DM_GPIO and legacy GPIO code. For those, switch to including asm/gpio.h (if it wasn't included already). Right now, this header provides both sets of functions, because ARCH_SUNXI selects GPIO_EXTRA_HEADER. This will still be the right header to include once the DM_GPIO migration is complete and GPIO_EXTRA_HEADER is no longer needed. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-11gpio: sunxi: Remove the sunxi_name_to_gpio_bank functionSamuel Holland1-1/+0
The only caller of this function was the MMC pinmux code, which used it to parse a string given from a Kconfig symbol. As the Kconfig symbol has been converted to a Boolean, this function is no longer needed. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-11sunxi: Simplify MMC pinmux selectionSamuel Holland2-21/+4
Only one board, Yones Toptech BD1078, actually uses a non-default MMC pinmux. All other uses of these symbols select the default value or an invalid value. To simplify things, remove support for the unused pinmux options, and convert the remaining option to a Boolean. This allows the pinmux to be chosen by the preprocessor, instead of having the code parse a string at runtime (for a build-time option!). Not only does this reduce code size, but it also allows this Kconfig option to be used in a table-driven DM pinctrl driver. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-11clk: sunxi: Move header out of arch directorySamuel Holland1-100/+0
The CCU header is only used by the DM drivers, not any platform code. Its current location adds an artificial dependency on CONFIG_ARM and ARCH_SUNXI, which will be problematic when adding the CCU driver for a RISC-V sunxi platform. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-08image: Drop IMAGE_ENABLE_OF_LIBFDTSimon Glass5-8/+8
Add a host Kconfig for OF_LIBFDT. With this we can use CONFIG_IS_ENABLED(OF_LIBFDT) directly in the tools build, so drop the unnecessary indirection. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2021-10-08image: Drop IMAGE_ENABLE_FITSimon Glass1-1/+1
Make use of the host Kconfig for FIT. With this we can use CONFIG_IS_ENABLED(FIT) directly in the host build, so drop the unnecessary indirection. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2021-10-08arm: dts: stm32: Add i2c-analog-filter property in I2C nodes for stm32h743Patrice Chotard1-0/+4
Add i2c-analog-filter property in I2C nodes to enable analog filter feature. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-10-08arm: dts: stm32: Add i2c-analog-filter property in I2C nodes for stm32f746Patrice Chotard1-0/+4
Add i2c-analog-filter property in I2C nodes to enable analog filter feature. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-10-08arm: mvebu: dts: m801: correct CP1 pinctrlRobert Marko1-21/+15
Current CP1 pinctrl that is set on the Puzzle M801 is incorrect. CP1 pins are only used for the SMI bus and the MSS I2C, all other pins are just GPIO-s. Due to this being set completely wrong, the pinctrl was actually ended up being hardcoded in the board_early_init_f() step so that SMI would work. That is obviously not the right thing to do, so convert the register hex values that were being written to individual pin modes and set it in the DTS. Add the SMI pins to the CP1 MDIO node as otherwise CP1 pinctrl does not get probed without an consumer. Fixes: 2ae2b8a2 ("arm: mvebu: Initial iEi Puzzle-M801 support") Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Stefan Roese <sr@denx.de>
2021-10-08arm: mvebu: Select SPL_SKIP_LOWLEVEL_INIT on ARMADA_32BITStefan Roese1-0/+1
Select SPL_SKIP_LOWLEVEL_INIT on 32bit Armada platforms via Kconfig, as this was removed from mach/config.h in a2ac2b96 ("Convert CONFIG_SKIP_LOWLEVEL_INIT et al to Kconfig"). Signed-off-by: Stefan Roese <sr@denx.de> Fixes: a2ac2b96 ("Convert CONFIG_SKIP_LOWLEVEL_INIT et al to Kconfig") Cc: Tom Rini <trini@konsulko.com> Cc: Marek Behún <kabel@kernel.org> Cc: Pali Rohár <pali@kernel.org> Tested-by: Pali Rohár <pali@kernel.org>
2021-10-08arm: mvebu: a38x: serdes: Update comment about PCIE*_ENABLE_* definesPali Rohár1-1/+1
These are part of SOC_CONTROL_REG1 register, not PEX_CAPABILITIES_REG. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
2021-10-08arm: mvebu: a38x: serdes: Remove unused PCIe macros and functionsPali Rohár2-188/+0
Remove unused PCIe functions from SerDes code. They are unused and are duplicated either from generic PCIe code or from pci_mvebu.c. Remove also unused PCIe macros from SerDes code. They are just obfuscated variants of standards macros in include/pci.h or in pci_mvebu.c. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
2021-10-08arm: mvebu: a38x: serdes: Don't configure PCIe cards in SerDes init codePali Rohár1-127/+1
This code is trying to parse PCIe config space of PCIe card connected on the other end of link and then is trying to force 5.0 GT/s speed via Target Link Speed bits in PCIe Root Port Link Control 2 Register on the local part of link if it sees that card supports 5.0 GT/s via Max Link Speed bits in Link Capabilities Register. The code is incorrect for more reasons: - Accessing config space of an endpoint card cannot be done immediately. If the PCIe link is not up, reading vendor/device ID registers will return all ones. - Parsing is incomplete, so it can cause issues even for working cards. Moreover there is no need to force speed to 5.0 GT/s via Target Link Speed bits on PCIe Root Port Link Control 2 Register. Hardware changes speed from 2.5 GT/s to 5.0 GT/s autonomously when it is supported. Most importantly, this code does not change link speed at all, since because after updating Target Link Speed bits on PCIe Root Port Link Control 2 Register, it is required to retrain the link, and the code for that is completely missing. The code was probably needed for making buggy endpoint cards work. Such a workaround, though, should be implemented via PCIe subsystem (via quirks, for example), as buggy cards could also affect other PCIe controllers. Note that this code is fully unrelated to a38x SerDes code and really should not have been included in SerDes initialization. Usage of magic constants without names and comments made this SerDes code hard to read and understand. Remove this PCIe application code from low level SerDes code. As this code is configuring only 5.0 GT/s part, in the worst case, it could leave buggy cards at the initial speed of 2.5 GT/s (if somehow before this change they could have been "upgraded" to 5.0 GT/s speed even with missing link retraining). Compliant cards which just need longer initialization should work better after this change. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
2021-10-08arm: mvebu: a38x: serdes: Don't overwrite PCI device IDPali Rohár1-27/+0
PCI device ID is part of the PCIe controller SoC / revision. For Root Complex mode (which is the default and the only mode supported currently by U-Boot and Linux kernel), it is PCI device ID of PCIe Root Port device. If there is some issue with this device ID, it should be set / updated by PCIe controller driver (pci_mvebu.c), as this register resides in address space of the controller. It shouldn't be done in SerDes initialization code. In the worst case (a specific board for example) it could be done via U-Boot's weak function board_pex_config(). But it should not be overwritten globally for all A38x devices. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
2021-10-08arm: mvebu: a38x: serdes: Don't set PCIe Common Clock ConfigurationPali Rohár1-15/+0
Enabling Common Clock Configuration bit in PCIe Root Port Link Control Register should not be done unconditionally. It is enabled by operating system as part of ASPM. Also after enabling Common Clock Configuration it is required to do more work, like retraining link. Some cards may be broken due to this incomplete Common Clock Configuration and some cards are broken and do not support ASPM at all. Remove this incomplete code for Common Clock Configuration. It really should not be done in SerDes code as it is not related to SerDes, but to PCIe subsystem. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
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