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2019-12-03arm: pxa: Drop pxa_wait_ticks()Simon Glass1-8/+4
This function has a similar name to the common wait_ticks(). It is only used in one place and seems small enough to drop. Inline it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-03common: Move some time functions out of common.hSimon Glass8-0/+8
These functions belong in time.h so move them over and add comments. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-03common: Move serial functions out of common.hSimon Glass1-0/+1
These functions belong in serial.h so move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-03Move strtomhz() to vsprintf.hSimon Glass21-0/+21
At present this function sits in its own file but it does not really justify it. There are similar string functions in vsprintf.h, so move it there. Also add the missing function comment. Use the vsprintf.h include file explicitly where needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-03crc32: Use the crc.h header for crc functionsSimon Glass2-0/+2
Drop inclusion of crc.h in common.h and use the correct header directly instead. With this we can drop the conflicting definition in fw_env.h and rely on the crc.h header, which is already included. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-03status_led: Tidy up the code styleSimon Glass1-1/+1
There are a few whitespace problems with this code. Tidy them up. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-03Drop CONFIG_SHOW_ACTIVITYSimon Glass1-13/+0
This feature is not enabled by any board. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
2019-12-03common: Move older CPU functions to their own headerSimon Glass6-0/+6
These should be moved to driver model, but in the meantime, move them out of the common header to help reduce its size. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-11-28Merge git://git.denx.de/u-boot-socfpgaTom Rini2-1/+13
- Assorted Gen5 fixes
2019-11-28Merge tag 'mmc-11-27-2019' of ↵Tom Rini6-57/+0
https://gitlab.denx.de/u-boot/custodians/u-boot-mmc - fsl_esdhc update and some cleanup in ls1021a/mpc83xx code - mmc tmio sdhi update for hs400
2019-11-28Merge tag 'u-boot-stm32-20191126' of ↵Tom Rini27-530/+670
https://gitlab.denx.de/u-boot/custodians/u-boot-stm - Solve warning for stih410-b2260 - Device tree alignment on v5.4-rc4 for all stm32 boards - Correct the eMMC pin configuration on stm32mp157c-ev1 - Add DFU and SPI-NAND support for stm32mp1 board
2019-11-28Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xxTom Rini9-0/+56
- powerpc: Fix DM_MMC related build warnings by adding eSDHC device module support for T4240RDB, T2080RDB, T1042D4RDB, T1024RDB, P5040DS, P4080DS, P3041DS, P2041RDB, P2020RDB, P1020RDB platforms
2019-11-27mpc83xx: remove unused clock.hYangbo Lu1-22/+0
The clock.h was to define mxc_get_clock() providing clock value to fsl_esdhc driver. Since fsl_esdhc driver is using global data gd->arch.sdhc_clk directly now, we can remove this file. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-27arm: drop eSDHC clock getting in mxc_get_clock() for layerscapeYangbo Lu5-35/+0
Although layerscape platforms reuse mxc_get_clock() of i.MX platforms, eSDHC clock getting do not have to use it. It uses global data gd->arch.sdhc_clk directly in fsl_esdhc driver. Even there are more than one eSDHC controllers on SoC, they use same reference clock. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-26ARM: dts: stm32: update eMMC configuration for stm32mp157c-ev1Patrick Delaunay4-8/+66
Update the sdmmc2 node for eMMC support on eval board stm32mp157c-ev1. - update slew-rate for pin configuration - update "vqmmc-supply" - remove "st,sig-dir" - add mandatory "pinctrl-names" - add "mmc-ddr-3_3v" This patch solve the eMMC detection issue for command "mmc dev 1". Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-11-26ARM: dts: stm32: DT alignment with kernel v5.4-rc4Patrick Delaunay10-14/+237
Device tree and binding alignment with kernel v5.4-rc4 Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2019-11-26ARM: dts: stm32: DT alignment with kernel v5.3Patrick Delaunay20-508/+367
Device tree and binding alignment with kernel v5.3 and converted to SPDX. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2019-11-25Merge tag 'rpi-next-2020.01' of https://github.com/mbgg/u-bootTom Rini10-19/+167
- add RPi4 upstream compatible to pinctrl - fix boot banner on RPi3/4 - add support for one binary on RPi3/4
2019-11-25ARM: socfpga: Unreset NAND in SPL on Gen5Marek Vasut1-0/+7
In case the SPL on Gen5 loads U-Boot from NAND, unreset the NAND IP explicitly in the platform code as the denali-spl driver is not aware of DM at all. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dalon Westergreen <dwesterg@gmail.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-11-25ARM: socfpga: Add ArriaV ST/SX IDMarek Vasut1-0/+2
Add new FPGA ID for ArriaV ST/D3 or SX/B3 . Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dalon Westergreen <dwesterg@gmail.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-11-25ARM: socfpga: Purge pending transactions upon enabling bridges on Gen5Marek Vasut1-0/+3
On Gen5, when the FPGA is loaded and there was some prior interaction between the HPS and the FPGA via bridges (e.g. Linux was running and using some of the IPs in the FPGA) followed by warm reset, it has been observed that there might be outstanding unfinished transactions. This leads to an obscure misbehavior of the bridge. When the bridge is enabled again in U-Boot and there are outstanding transactions, a read from within the bridge address range would return a result of the previous read instead. Example: => bridge enable ; md 0xff200000 1 ff200000: 1234abcd => bridge enable ; md 0xff200010 1 ff200010: 5678dcba <------- this is in fact a value which is stored in a memory at 0xff200000 => bridge enable ; md 0xff200000 1 ff200000: 90effe09 <------- this is in fact a value which is stored in a memory at 0xff200010 and so it continues. Issuing a write does lock the system up completely. This patch opens the FPGA bridges in 'bridge enable' command, the tears them down again, and then opens them again. This allows these outstanding transactions to complete and makes this misbehavior go away. However, it is not entirely clear whether this is the correct solution. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dalon Westergreen <dwesterg@gmail.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-11-25ARM: socfpga: Actually put bridges into reset on Gen5 in bridge disableMarek Vasut1-1/+1
On Gen5, the 'bridge disable' command write 0x0 to brgmodrst register, which releases all bridges from reset, instead of putting all bridges into reset. Fix this by inverting the mask and actually putting the bridges into reset. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dalon Westergreen <dwesterg@gmail.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-11-25arch: powerpc: add eSDHC node to t4240 dtsYinbo Zhu1-0/+6
Add eSDHC node to t4240 dts Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-25arch: powerpc: add eSDHC node to t104x dtsYinbo Zhu1-0/+6
Add eSDHC node to t104x dts Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-25arch: powerpc: add eSDHC node to t102x dtsYinbo Zhu1-0/+6
Add eSDHC node to t102x dts Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-25arch: powerpc: add eSDHC node to p5040 dtsYinbo Zhu1-0/+6
Add eSDHC node to p5040 dts Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-25arch: powerpc: add eSDHC node to p4080 dtsYinbo Zhu1-0/+6
Add eSDHC node to p4080 dts Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-25arch: powerpc: add eSDHC node to p3041 dtsYinbo Zhu1-0/+6
Add eSDHC node to p3041 dts Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-25arch: powerpc: add eSDHC node to p2041 dtsYinbo Zhu1-0/+6
Add eSDHC node to p2041 dts Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-25arch: powerpc: add eSDHC node to p2020 dtsYinbo Zhu1-0/+7
Add eSDHC node to p2020 dts Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-25arch: powerpc: add eSDHC node to p1020 dtsYinbo Zhu1-0/+7
Add eSDHC node to p1020 dts Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-24ARM: defconfig: add unified config for RPi3 and RPi4Matthias Brugger1-0/+7
Provide a defconfig which allows us to boot Raspberrry Pi 4 and Raspberry Pi 3 Model B/B+ Instead of using the embedded DTB as done in RPi3 we use the devicetree provided by the firmware. Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2019-11-24ARM: bcm283x: Set memory map at run-timeMatthias Brugger1-0/+92
For bcm283x based on arm64 we also have to change the mm_region. Add assign this in mach_cpu_init() so we can create now one binary for RPi3 and RPi4. Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2019-11-24ARM: bcm283x: Set rpi_bcm283x_base at run-timeMatthias Brugger2-8/+18
As part of the effort to create one binary for several bcm83x SoCs we read the IO base address from device-tree. Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2019-11-24ARM: bcm283x: Move BCM283x_BASE to a global variableMatthias Brugger8-9/+52
We move the per SOC define BCM283x_BASE to a global variable. This is a first step to provide a single binary for several bcm283x SoCs. Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2019-11-24arm: dts: bcm283x: Rename U-Boot fileMatthias Brugger1-0/+0
Rename the file bcm283x-uboot.dtsi so that it get automatically include through the scripts/Makefile.lib using $(CONFIG_SYS_SOC))-u-boot.dtsi Without this uarts and pincontroller miss the property dm-pre-reloc and the first call to bcm283x_mu_serial_ofdata_to_platdata() fails as the pins are not set correctly. As a result the U-Boot banner isn't shown on boot. Before commmit 143256b353 ("fdt: update bcm283x device tree sources to Linux 5.1-rc6 state") we included bcm283x-uboot.dtsi directly in the device-tree file. Which got deleted by the metioned commit. This is a much robuster solution. Reported-by: Tom Rini <trini@konsulko.com> Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Tested-by: Tom Rini <trini@konsulko.com> [RPi 3, 32b and 64b modes] Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2019-11-24fdt: fix bcm283x dm-pre-reloc definitionsMatthias Brugger1-4/+0
In commmit 143256b353 ("fdt: update bcm283x device tree sources to Linux 5.1-rc6 state") we deleted the label for the node soc from bcm283x.dtsi As we don't need to add the property dm-pre-reloc to the soc node, we can delete it from bcm283x-uboot.dtsi Tested-by: Tom Rini <trini@konsulko.com> [RPi 3, 32b and 64b modes] Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2019-11-24Merge tag 'u-boot-rockchip-20191124' of ↵Tom Rini4-54/+113
https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - Clean vid/pid in Kconfig and add fastboot for rk3399 - add 'u-boot, spl-fifo-mode' for mmc - Use FIT generator for rk3229 optee and rk3368 ATF - fan53555: add support for Silergy SYR82X and SYR83X
2019-11-23arm: fix -march for ARM11Heinrich Schuchardt1-2/+2
In GCC 9 support for the Armv5 and Armv5E architectures (which have no known implementations) has been removed, cf. https://gcc.gnu.org/gcc-9/changes.html ARM11 is an armv6 implementation. So change the architecture flag for the compiler to armv6 for ARM11. Suggested-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2019-11-23rockchip: px30: enable spl-fifo-mode for both emmc and sdmmc on evbHeiko Stuebner1-2/+5
As part of loading trustedfirmware, the SPL is required to place portions of code into the socs sram but the mmc controllers can only do dma transfers into the regular memory, not sram. The results of this are not directly visible in u-boot itself, but manifest as security-relate cpu aborts during boot of for example Linux. There were a number of attempts to solve this elegantly but so far discussion is still ongoing, so to make the board at least boot correctly put both mmc controllers into fifo-mode, which also circumvents the issue for now. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-11-23rockchip: Setup dwc3_device (for non-dm gadgets)Jagan Teki1-2/+30
Setup dwc3_device structure for non-dm gadgets, which is used in rk3399 platforms. dwc3_device would have basic regbase, dr_mode, high speed and 16-bit UTMI+ etc. Cc: Marek Vasut <marex@denx.de> Tested-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> (Fix to use CONFIG_USB_DWC3_GADGET instead of CONFIG_USB_DWC3) Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-23rockchip: Convert to use FIT generator for opteeKever Yang2-50/+78
Use generator script so that we can use environment for TEE source. $TEE for tee.bin, and if file not exist, the script can report a warning, and meke the build success without a error. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-22Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2-4/+7
- Assorted fixes
2019-11-22Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini1-1/+0
- Assorted Gen3 fixes
2019-11-22arm: socfpga: stratix10: Add alias for gmac0 in S10 dtsOoi, Joyce1-0/+1
Add 'ethernet0' as alias for 'gmac0' in S10 device tree. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Ooi, Joyce <joyce.ooi@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-11-22arm: dts: Stratix10: change pad skew values for EMAC0 PHY driverOoi, Joyce1-1/+1
The HPS EMAC0 drive strength is changed to 4mA because the initial 8mA drive strength has caused CE test to fail. This requires changes on the pad skew for EMAC0 PHY driver. Based on several measurements done, Tx clock does not require the extra 0.96ns delay which was needed in Arria10. Signed-off-by: Ooi, Joyce <joyce.ooi@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-11-21env: Finish migration of common ENV optionsTom Rini1-1/+1
- In ARMv8 NXP Layerscape platforms we also need to make use of CONFIG_SYS_RELOC_GD_ENV_ADDR now, do so. - On ENV_IS_IN_REMOTE, CONFIG_ENV_OFFSET is never used, drop the define to 0. - Add Kconfig entry for ENV_ADDR. - Make ENV_ADDR / ENV_OFFSET depend on the env locations that use it. - Add ENV_xxx_REDUND options that depend on their primary option and SYS_REDUNDAND_ENVIRONMENT - On a number of PowerPC platforms, use SPL_ENV_ADDR not CONFIG_ENV_ADDR for the pre-main-U-Boot environment location. - On ENV_IS_IN_SPI_FLASH, check not for CONFIG_ENV_ADDR being set but rather it being non-zero, as it will now be zero by default. - Rework the env_offset absolute in env/embedded.o to not use CONFIG_ENV_OFFSET as it was the only use of ENV_OFFSET within ENV_IS_IN_FLASH. - Migrate all platforms. Cc: Wolfgang Denk <wd@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: uboot-stm32@st-md-mailman.stormreply.com Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-11-21socfpga: fix include guard in misc.h (arch vs. global)Simon Goldschmidt1-3/+3
The file arch/arm/mach-socfpga/include/mach/misc.h used the same include guard as the global include/misc.h. Fix this by giving the arch file an arch prefix. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-11-21arm: dts: Stratix10: Fix memory node address and size cellsLey Foon Tan1-0/+2
Add #address-cells and #size-cells to memory node to fix incorrect memory size decoding in recent Uboot version. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-11-20Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xxTom Rini7-10/+54
- Fix CONFIG_AHCI related build warning for P2041, P3041, P5040, T102x, T104x, T4240 platforms
generated by cgit v1.2.3 (git 2.39.0) at 2024-07-24 06:55:37 +0300