summaryrefslogtreecommitdiff
path: root/arch
AgeCommit message (Collapse)AuthorFilesLines
2021-11-26sandbox: poweroff in efi_system_reset()Heinrich Schuchardt1-2/+4
efi_system_reset() should exit if called with EFI_RESET_SHUTDOWN. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-11-19arm64: Add missing GD_FLG_SKIP_RELOC handlingMarek Vasut1-0/+4
In case U-Boot enters relocation with GD_FLG_SKIP_RELOC, skip the relocation. The code still has to set up new_gd pointer and new stack pointer. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com>
2021-11-16Merge branch '2021-11-15-assorted-fixes'Tom Rini2-3/+3
- Rename "tqc" to "tq" and related updates - Assorted minor ARM updates, build updates and documentation updates
2021-11-16Merge tag 'xilinx-for-v2022.01-rc3' of ↵Tom Rini5-8/+256
https://source.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2022.01-rc3 sdhci: - Fix emmc mini case with missing firmware interface zynqmp: - Restore JTAG interface if required - Allow overriding board name - Add support for DLC21 - Fix one fallthrought statement description - Use config macro instead of name duplication - Save multiboot to variable firmware: - Handle ipi_req errors better - Use local buffer in case user doesn't need it instead of NULL/0 location spi: - gqsi: Fix write issue at low frequencies net: - gem: Disable broadcasts
2021-11-15arm: Fix bad memcpy.S str8w macro argument countPierre-Clément Tosi1-1/+1
Remove the extra (empty) argument passed to str8w, causing the following error: <instantiation>:40:47: error: too many positional arguments str8w r0, r3, r4, r5, r6, r7, r8, r9, ip, , abort=19f ^ u-boot/arch/arm/lib/memcpy.S:240:5: note: while in macro instantiation 17: forward_copy_shift pull=16 push=16 ^ Note: no functional change intended. Fixes: d8834a1323af ("arm: Use optimized memcpy and memset from linux") Signed-off-by: Pierre-Clément Tosi <ptosi@google.com>
2021-11-15board: tq: fix spelling of "TQ-Systems"Matthias Schiffer1-1/+1
"TQ-Systems" is written with a dash. Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
2021-11-15board: rename "tqc" vendor to "tq"Matthias Schiffer1-1/+1
The subdivision name "TQ Components" hasn't been in use for a long time. Rename the vendor directory to "tq", which also matches our Device Tree vendor prefix. Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
2021-11-12Remove CONFIG_SERIAL_MULTITom Rini1-1/+0
This symbol has been functionally dead for a long time. Remove the last and recent re-introductions of setting it, and update the whitelist so it will not be re-introduced again. Signed-off-by: Tom Rini <trini@konsulko.com>
2021-11-12Convert CONFIG_FSL_LAYERSCAPE to KconfigTom Rini1-0/+2
This converts the following to Kconfig: CONFIG_FSL_LAYERSCAPE Signed-off-by: Tom Rini <trini@konsulko.com>
2021-11-12ARM: dts: am335x-chiliboard: add /chosen/tick-timerMarcin Niestroj1-1/+2
Commit 4b2be78ab66c ("time: Fix get_ticks being non-monotonic") has broken boot on chiliboard platform, as it requires '/chosen/tick-timer' in device-tree. This resulted in following panic message: Could not initialize timer (err -19) Provide missing chosen property in device-tree to fix chiliboard support. Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
2021-11-11Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriqTom Rini39-618/+1525
- device-tree sync-up with Linux for ls1028a - fixes/update in fsl-ddr driver, fsl-validate, lx2162a, fsl-mc, spintable code, configs, qspi node, pci - enable EFI_SET_TIME support in sl28 - powerpc: Drop -mstring
2021-11-10Merge tag 'u-boot-stm32-20211110' of ↵Tom Rini16-312/+73
https://source.denx.de/u-boot/custodians/u-boot-stm - DHSOM update: - Remove nWP GPIO hog - Increase SF bus frequency to 50Mhz and enable SFDP - Disable video output for DHSOM - Disable EFI - Enable DFU_MTD support - Create include file for STM32 gpio driver private data - Split board and SOC STM32MP15 configuration - Device tree alignement with v5.15-rc6 for STM32MP15 - Add binman support for STM32MP15x - Normalise newlines for stm32prog - Update OTP shadow registers in SPL
2021-11-10stm32mp15: tidy up #ifdefs in cpu.cPatrick Delaunay1-19/+15
We should avoid #ifdef in C modules and the unused functions are eliminated by the linker. Use the more readable IS_ENABLE() instead. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-11-10stm32mp15: replace CONFIG_TFABOOT when it is possiblePatrick Delaunay2-18/+12
In some part of STM32MP15 support the CONFIG_TFABOOT can be replaced by other config: CONFIG_ARMV7_PSCI and CONFIG_ARM_SMCCC. This patch also simplifies the code in cpu.c, stm32mp1_ram.c and clk_stml32mp1.c as execution of U-Boot in sysram (boot without SPL and without TFA) is not supported: the associated initialization code is present only in SPL. This cleanup patch is a preliminary step to support SPL load of OP-TEE in secure world, with SPL in secure world and U-Boot in no-secure world. Reported-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-11-10stm32mp15: remove configs dependency on CONFIG_TFABOOTPatrick Delaunay1-6/+2
Remove the dependency on CONFIG_TFABOOT in stm32mp Kconfig - always activate the ARCH config: CONFIG_ARCH_SUPPORT_PSCI and CONFIG_CPU_V7_HAS_NONSEC - CONFIG_ARMV7_NONSEC is deactivated in trusted defconfig - the correct sysreset driver is activated in each defconfig: CONFIG_SYSRESET_PSCI or SYSRESET_SYSCON Reported-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-11-10arm: stm32mp: bsec: Update OTP shadow registers in SPLPatrick Delaunay2-3/+10
Currently the upper OTP (after 57) are shadowed in U-Boot proper, when TFABOOT is not used. This choice cause an issue when U-Boot is not executed after SPL, so this BSEC initialization is moved in SPL and no more executed in U-Boot, so it is still executed only one time. After this patch this BSEC initialization is done in FSBL: SPL or TF-A. To force this initialization in all the case, the probe of the BSEC driver is forced in SPL in the arch st32mp function: spl_board_init(). Even if today BSEC driver is already probed in STM32MP15x clock driver clk_stm32mp1.c because get_cpu_type() is called in stm32mp1_get_max_opp_freq() function. Reported-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-11-10ARM: dts: stm32: Drop nWP GPIO hog on DHSOMMarek Vasut2-18/+0
The nWP GPIO hog was used to unlock the SPI NOR write protect when U-Boot used to operate the SPI NOR in 1-1-1 mode. Now that the SPI NOR is operated in 1-1-4 mode, the hog has adverse effects and causes transfer corruption, since the hogged pin is also the IO2 pin. Remove the hogs. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-11-10gpio: stm32: create include file for driver private dataPatrick Delaunay6-214/+0
The stm32 gpio driver private data are not needed in arch include files, they are not used by code except for stm32 gpio and pincontrol drivers, using the same IP; the defines for this IP is moved in a new file "stm32_gpio_priv.h" in driver/gpio. This patch avoids to have duplicated file gpio.h for each SOC in MPU directory mach-stm32mp and in each MCU directory arch-stm32* and allows to remove CONFIG_GPIO_EXTRA_HEADER for all STM32. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-11-10arm: dts: stm32mp15: alignment with v5.15-rc6Patrick Delaunay2-8/+8
Device tree alignment with Linux kernel v5.15-rc6 - Set {bitclock,frame}-master phandles on ST DKx - Add coprocessor detach mbox on stm32mp15x-dkx boards - Add coprocessor detach mbox on stm32mp157c-ed1 board Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-11-10stm32mp: add binman support for STM32MP15xPatrick Delaunay3-29/+30
Use binman to add the stm32image header on SPL binary for basic boot or on U-Boot binary when it is required, i.e. for TF-A boot without FIP support, when CONFIG_STM32MP15x_STM32IMAGE is activated. The "binman" tool is the recommended tool for specific image generation. This patch allows to suppress the config.mk file and it is a preliminary step to manage FIT generation with binman. The init_r parsing of U-Boot device tree to search the binman information is not required for STM32MP15, so the binman library can be removed in U-Boot (CONFIG_BINMAN_FDT is deactivated). Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-11-10stm32mp: stm32prog: Normalise newlinesWilliam Grant1-2/+1
The missing trailing newline could confuse check-config.sh if the definition of an option was on the first line of the next file that find(1) happened to return. Signed-off-by: William Grant <wgrant@ubuntu.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-11-09Merge https://source.denx.de/u-boot/custodians/u-boot-samsungTom Rini1-5/+6
[trini: Migrate CONFIG_EXYNOS7420 as part of merging, so espresso7420 still builds] Signed-off-by: Tom Rini <trini@konsulko.com>
2021-11-09armv8: layerscape: use memalign() to allocate spintable codeMichael Walle1-15/+14
Don't use efi_allocate_pages(). The allocated memory isn't carved out of the lmb allocations. The memory might then be allocated twice. Particulary, this might happened with the fdt_high/initrd_high feature which will relocate the fdt/ramdisk. This might then overlap with the spin table. Instead use memalign() which allocates on memory on the heap which is correctly carved out by lmb. Please note, that the memory is later reserved in the device tree as well as in the EFI memory map in ft_fixup_cpu() (in arch/arm/cpu/armv8/fsl-layerscape/fdt.c). Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09armv8: fsl-layerscape: rework the dwc3 snooping enable codeMichael Walle1-15/+13
Instead of looking at all USB (host) devices, just search all DWC3 device tree nodes. This will (1) fix a panic if of_match is zero and (2) also apply the fixup if the controller is in peripheral mode. Both happen when the DWC3 USB controller driver is used. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09arm: dts: sl28: sync dtbsMichael Walle6-92/+265
Copy the board device tree files from linux v5.14. On top of the v5.14 dtbs the changes of these two patches are included here which are needed for u-boot: https://lore.kernel.org/linux-devicetree/20210831134013.1625527-7-michael@walle.cc/ https://lore.kernel.org/linux-devicetree/20210831134013.1625527-8-michael@walle.cc/ At the time of this writing the patches were accepted and will be included in 5.15. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09arm: dts: ls1028a: sync the fsl-ls1028a.dtsi with linuxMichael Walle1-90/+770
Now that everything is prepared, copy the fsl-ls1028a.dtsi from the linux kernel v5.14.12. Notable changes: - second watchdog added - the number of chip selects of the SPI controller is now correct and reflects what the hardware offers - the LPUARTs have the correct clock parent - USB controllers are enabled by default, which was already the case before this sync because all board enabled all the USB controller nodes. A linux patch to fix this is pending. - the eSDHC controller changes from big-endian to little-endian, but that property seems to be not used at all. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09arm: dts: ls1028a: disable the PCIe controller by defaultMichael Walle4-0/+31
Disable the PCIe controllers by default, just like in the linux device tree. But there is one catch, for linux they are enabled in-place by the bootloader. Obviously, this doesn't work for the bootloader. Thus we explicitly enable the controllers in the -u-boot.dtsi files. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09arm: dts: ls1028a: move the PCI I/O window to matchMichael Walle1-2/+2
To make the synchronization of the u-boot device tree with the one from linux easier, move the I/O window to the one which is specified in the linux device tree. The actual value shouldn't matter as long as it mapped to the corresponding memory window of the PCIe controller which is a 32GiB window at 80_0000_0000h (first controller) or 88_0000_0000h (second controller). Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09arm: dts: ls1028a: remove num-lanes in the PCIe controller nodesMichael Walle1-2/+0
This property is unused in the layerscape PCIe controller driver and not present in the linux device tree. Remove it to be similarly. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09pci: layerscape: add official ls1028a binding supportMichael Walle1-12/+8
The official bindind of the PCIe controller of the ls1028a has the following compatible string: compatible = "fsl,ls1028a-pcie"; Additionally, the resource names and count are different. Update the driver to support this binding and change the entry in the ls1028a device tree. Cc: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09usb: xhci: fsl: add new compatible fsl,ls1028a-dwc3Michael Walle1-2/+2
The official ls1028a binding of the driver uses the following as compatibles: compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; Change the ls1028a device tree and add this new compatible to the fsl specific xhci driver, otherwise the generic dwc3 driver will be used with the compatibles above. Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Marek Vasut <marex@denx.de> Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09scsi: ceva: rename the resource name to match the linux kernel oneMichael Walle6-6/+6
The driver will look for a named resource "ecc-addr", but this isn't the official binding. In fact, the official device tree binding documentation doesn't mention any resource names at all. But it is safe to assume that it's the linux ones we have to use if we want to be compatible with the linux device tree. Thus rename "ecc-addr" to "sata-ecc" and convert all the users in u-boot. While at it, also rename "sata-base" to "ahci" although its not used at all. This change doesn't affect the SATA controller on the ZynqMP. Cc: Michal Simek <monstr@monstr.eu> Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09serial: lpuart: add new compatible fsl, ls1028a-lpuartMichael Walle1-12/+6
The official ls1028a binding of the driver uses the following as compatibles: compatible = "fsl,ls1028a-lpuart"; Add the missing compatible to the driver and update the device tree. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09spi: fsl_dspi: rename num-cs to spi-num-chipselectsMichael Walle9-17/+17
The official devicetree bindings specifies spi-num-chipselects as the name. Use it. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09spi: fsl_dspi: add new compatible fsl, ls1021a-v1.0-dspiMichael Walle1-3/+3
The official ls1028a binding of the driver uses the following as compatibles: compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; Add the missing compatible to the driver and update the device tree. We can use the fallback "fsl,ls1021a-v1.0-dspi", because the endianness is determined by the little-endian property and not by the compatible string itself. Further, we won't need and specific details on the DMA configuration (which is different on the LS1021A). If it's ever needed, we can later add the more specific "fsl,ls1028a-dspi" compatible to the driver. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09watchdog: sp805_wdt: use correct compatible stringMichael Walle2-3/+3
According to the linux device tree specification the compatible string is: compatible = "arm,sp805", "arm,primecell"; Fix all users in u-boot. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09arm: dts: ls1028a: update the labelsMichael Walle23-81/+81
Update the labels of the nodes to match the kernel ones. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Tested-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09arm: dts: ls1028a: move the iRC node and its devices into /socMichael Walle1-99/+103
While inserting them into the new location, keep them sorted by the register base offset just like in the linux kernel device tree. While at it fix the indentation. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09arm: dts: ls1028a: move the watchdog node into /socMichael Walle1-5/+5
While inserting it into the new location, keep it sorted by the register base offset just like in the linux kernel device tree. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09arm: dts: ls1028a: move the PCIe controller nodes into /socMichael Walle1-32/+32
While inserting them into the new location, keep them sorted by the register base offset just like in the linux kernel device tree. While at it fix the indentation. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09arm: dts: ls1028a: move SATA and USB controller nodes into /socMichael Walle1-25/+25
While inserting them into the new location, keep them sorted by the register base offset just like in the linux kernel device tree. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09arm: dts: ls1028a: move the GPIO controller nodes into /socMichael Walle1-33/+33
While inserting them into the new location, keep them sorted by the register base offset just like in the linux kernel device tree. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09arm: dts: ls1028a: move the low-power UART nodes into /socMichael Walle1-60/+60
While inserting them into the new location, keep them sorted by the register base offset just like in the linux kernel device tree. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09arm: dts: ls1028a: move the UART controller nodes into /socMichael Walle1-16/+16
While inserting them into the new location, keep them sorted by the register base offset just like in the linux kernel device tree. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09arm: dts: ls1028a: move the SPI and eSDHC controller nodes into /socMichael Walle1-58/+58
While inserting them into the new location, keep them sorted by the register base offset just like in the linux kernel device tree. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09arm: dts: ls1028a: move the FlexSPI controller nodeMichael Walle1-13/+13
While inserting it into the new location, keep it sorted by the register base offset just like in the linux kernel device tree. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09arm: dts: ls1028a: move I2C controller nodes into /socMichael Walle12-115/+115
While inserting them into the new location, keep them sorted by the register base offset just like in the linux kernel device tree. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09arm: dts: ls1028a: move the clockgen node into /socMichael Walle1-7/+7
Populate the /soc node with the first device node. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09arm: dts: ls1028a: add an empty /socMichael Walle2-0/+11
To keep the device tree similar to the linux kernel one, we need to move all CCSR related devices into the /soc node. To keep the patches easy to review, we initially add an empty /soc node and populate it piece by piece. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09arm: dts: ls1028a-{rdb, qds}: remove dm-pre-reloc propertyMichael Walle2-2/+0
Nowadays, both boards boot using the TF-A BL1/BL2 and SPL isn't used at all. The property is not needed, remove it. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
generated by cgit v1.2.3 (git 2.39.0) at 2024-08-01 04:45:41 +0300