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2019-02-16usb: Rename SPL_USB_SUPPORT to SPL_USB_STORAGEAbel Vesa2-2/+2
Since there is the SPL_USB_HOST_SUPPORT for enabling USB support in SPL, makes more sense to rename the SPL_USB_SUPPORT as SPL_USB_STORAGE. Everything that is not part of the usb storage support in SPL is now build under SPL_USB_HOST_SUPPORT. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-02-15ARM: dts: imx6ul-lite*: add DTS files for liteSOM and liteboardMarcin Niestroj3-0/+235
Import liteSOM and liteboard dts files from Linux v4.20. They will be used after transition to driver model and device-tree based boot. Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
2019-02-15ddr: vybrid: Add calibration code to memory controler's (DDRMC) setup codeLukasz Majewski1-0/+5
This patch extends the vf610 DDR memory controller code to support SW leveling. Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Stefan Agner <stefan.agner@toradex.com>
2019-02-15ddr: vybrid: Provide code to perform on-boot calibrationLukasz Majewski4-0/+400
This patch provides the code to calibrate the DDR's DQS to DQ signals (RDLVL). It is based on: VFxxx Controller Reference Manual, Rev. 0, 10/2016, page 1600 10.1.6.16.4.1 "Software Read Leveling in MC Evaluation Mode" and NXP's community thread: "Vybrid: About DDR leveling feature on DDRMC." https://community.nxp.com/thread/395323 Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-02-15ddr: vybrid: Add DDRMC calibration related registers (DQS to DQ)Lukasz Majewski1-1/+13
This commit provides extra defines needed for DDR memory controller calibration (read leveling performing). Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Stefan Agner <stefan.agner@toradex.com>
2019-02-13arm: Leave smccc calls in .text when efi_loader=nAlexander Graf2-0/+4
Commit 81ea00838c6 ("efi_loader: PSCI reset and shutdown") put the SMCCC assembly code into the efi specific code section. This is wrong when we do not have EFI_LOADER enabled, as that strips efi runtime sections from the output binary Reported-by: Michal Simek <monstr@monstr.eu> Reported-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Tested-by: Michal Simek <monstr@monstr.eu> Fixes: 81ea00838c6 ("efi_loader: PSCI reset and shutdown") Signed-off-by: Alexander Graf <agraf@suse.de>
2019-02-13x86: do not use i386 code for x86_64 memory functionsHeinrich Schuchardt2-9/+24
arch/x86/lib/string.c contains assembler implementations of memcpy(), memmove(), and memset() written for i386. Don't use it on x86_64. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2019-02-13efi_loader: refactor switch to non-secure modeHeinrich Schuchardt4-0/+113
Refactor the switch from supervisor to hypervisor to a new function called at the beginning of do_bootefi(). Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2019-02-13efi_selftest: allow building on ARMv7-MHeinrich Schuchardt1-1/+5
ARMv7-M only supports the Thumb instruction set. Our current crt0 code does not support it. With the patch we can build all unit tests of the EFI subsystem that do not require crt0. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2019-02-12x86: tangier: Add initial ACPI support for PMIC deviceAndy Shevchenko1-0/+87
Basin Cove PMIC is connected to I2C0 bus which is hidden from the OS and access is going via SCU device, enumerated via PCI. For now, we add just a minimum support of PMIC device to allow enabling, e.g. USB OTG, in the OS. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-12x86: Use the existing GDT in the ROM for 64-bit U-Boot properBin Meng1-14/+0
It is unnecessary to use a RAM version GDT for 64-bit U-Boot proper. In fact we can just use the ROM version directly, which not only eliminates the risk of being overwritten by application, but also removes the complexity of patching the cpu_call64(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-02-12x86: Don't copy the cpu_call64() function to a hardcoded addressBin Meng2-3/+12
Before jumping to 64-bit U-Boot proper, SPL copies the cpu_call64() function to a hardcoded address 0x3000000. This can have potential conflicts with application usage. Switch the destination address to be allocated from the heap to avoid such risk. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-02-12x86: Change 4-level page table base address to low memoryBin Meng1-4/+2
At present the 4-level page table base address for 64-bit U-Boot proper is assigned an address that conflicts with CONFIG_LOADADDR. Change it to an address within the low memory range instead. Fixes crashes seen when 'dhcp' on QEMU x86_64 with "-net nic -net user,tftp=.,bootfile=u-boot". Reported-by: Alexander Graf <agraf@suse.de> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-02-11arm: mvebu: cf gt-8k: dts: add PCIe slot reset supportBaruch Siach1-0/+8
Describe the mini-PCIe slot gpio reset signal. This enables PCIe devices on Clearfog GT-8K. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2019-02-11arm: mvebu: mcbin: dts: fix PCIe reset polarityBaruch Siach1-1/+1
The PCIe slot PERST signal is active low. Fix the gpio signal description in the dts. This happened to work because the pcie_dw_mvebu driver sets the reset gpio level to 1 (high) to release the reset. The following commit will fix that. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2019-02-10Merge tag 'dm-pull-10feb19' of git://git.denx.de/u-boot-dmTom Rini6-22/+87
Samsung sound patches (applied for Samsung maintainer) Common sound support buildman environment support of-platdata documentation improvements
2019-02-09samsung: mmc: Drop old MMC init codeSimon Glass1-2/+0
Now that these boards use driver model we can drop the old code. At present s5p_mmc_init() is still used by goni and smdkv310 so cannot be removed unless we remove those boards. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
2019-02-09spring: Update flashmap detailsSimon Glass1-2/+39
Update the flashmap so that this board can be started over USB A-A. It is slightly different from snow. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-02-09spring: Update sound to use max98088 codecSimon Glass1-18/+18
Update the spring settings to use this codec, which is what it actually shipped with. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-02-09exynos: Convert to use CONFIG_BLKSimon Glass4-0/+30
Move all exynos boards over to use CONFIG_BLK. This converts s5p_goni also, but adding dummy functions for pinmux and peripheral ID. This will not function correctly, but gives the maintainer more time to convert the board if desired. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
2019-02-09arm: mach-k3: common: Clean up ATF image startup functionAndreas Dannenberg1-18/+10
Perform some cosmetic cleanup of the ATF image startup function, namely fixing a spelling mistake, capitalization of a few words, spacing, as well aligning how errors are printed and as using panic() for cases that were using a combination of printf() + hang(). Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-02-09dt: bcm63158: add watchdogPhilippe Reynes1-0/+17
This commit add watchdog and sysreset watchdog in the bcm63158 device tree. Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-02-09bcm963158: add initial supportPhilippe Reynes2-0/+32
This add the initial support of the broadcom reference board bcm963158 with a bcm63158 SoC. This board has 1 GB of ram, 512 MB of flash (nand), 2 usb port, 1 uart, 4 ethernet ports (LAN), 1 ethernet port (WAN). Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-02-09bcm63158: add initial supportPhilippe Reynes2-0/+91
This add the initial support of the broadcom bcm63158 SoC family, only the cpu, dram and uart are supported. Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-02-09dts: stm32mp1: clock tree updatePatrick Delaunay1-12/+15
- Add st,digbypass on clk_hse node (needed for board rev.C) - MLAHB/AHB max frequency increased from 200 to 209MHz, with: - PLL3P set to 208.8MHz for MCU sub-system - PLL3Q set to 24.57MHz for 48kHz SAI/SPI2S - PLL3R set to 11.29MHz for 44.1kHz SAI/SPI2S - PLL4P set to 99MHz for SDMMC and SPDIFRX - PLL4Q set to 74.25MHz for EVAL board Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-02-09dt: bcm6858: add watchdogPhilippe Reynes1-0/+17
This commit add watchdog and sysreset watchdog in the bcm6858 device tree. Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-02-09dt: bcm6838: add watchdogPhilippe Reynes1-0/+17
This commit add watchdog and sysreset watchdog in the bcm6838 device tree. Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-02-07Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2-1/+4
- SPI-NOR support
2019-02-07configs: Don't use SPI_FLASH_BAR as defaultVignesh R1-1/+0
Now that new SPI NOR layer uses stateless 4 byte opcodes by default, don't enable SPI_FLASH_BAR. For SPI controllers that cannot support 4-byte addressing, (stm32_qspi.c, fsl_qspi.c, mtk_qspi.c, ich.c, renesas_rpc_spi.c) add an imply clause to enable SPI_FLASH_BAR so as to not break functionality. Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-07sh: bitops: add hweight*() macrosVignesh R1-0/+4
Add hweight*() macros required for moving to new SF layer Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2019-02-06arm: dts: am33xx: introduce 'am33xx-u-boot.dtsi'Hannes Schmelzer1-0/+11
commit fdce9d35dc36 ("arm: dts: am33xx: Sync dts with Linux 4.20.0") did remove the "u-boot,dm-spl" flag from the 'ocp' bus which was introduced with commit 19aa4ac09db9 ("dts: am33xx: add u-boot, dm-spl to ocp bus") Due to this all boards having CONFIG_SPL_OF_CONTROL enabled are broken because they cannot bind/probe the boot-media interface during SPL stage. This commit introduces the 'am33xx-u-boot.dtsi' which is included with the auto include mechanism. The am33xx-u-boot-dtsi adds the important "u-boot,dm-pre-reloc" to the 'ocp bus' (the root bus of almost all peripherals, at least the bootable ones). The peripherials (mmc, spi, ...) needed during SPL stage need to be equipped with the 'u-boot,dm-pre-reloc' in their responsible dts file. Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
2019-02-05arm: mvebu: theadorable: Enable video / LCD support with the new DM driverStefan Roese1-0/+25
With the new DM_VIDEO support in the Armada XP LCD driver, this patch adds the needed DT node for the LCD controller to the theadorable dts file. This DT property is not added to the Armada XP dtsi files, as this LCD feature is pretty unusual for this SoC and I personally know of no other board that uses this controller. This patch also enables CONFIG_BMP_16BPP/24BPP/32BPP, as the "old" bmp command supported these BMP files. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Anatolij Gustschin <agust@denx.de> Acked-by: Anatolij Gustschin <agust@denx.de>
2019-02-05video: Armada XP: Move driver to DM_VIDEOStefan Roese1-12/+0
This patch moves the Armada XP video / LCD driver to DM_VIDEO. With this move, the legacy interface board_video_init() is removed from the theadorable board code (only user of this video driver). The support via DT will be added in a separate patch. This patch also enables DM_VIDEO for the theadorable board, as this is needed to not break git bisect'ability. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Anatolij Gustschin <agust@denx.de> Acked-by: Anatolij Gustschin <agust@denx.de>
2019-02-05arm64: mvebu: Add basic support for uDPU boardVladimir Vid3-0/+214
This adds initial support for micro-DPU (uDPU) board which is based on Armada-3720 SoC. micro-DPU is the single-port FTTdp "distribution point unit" made by Methode Electronics which offers complete modularity with replaceable SFP modules both for uplink and downlink (G.hn over twisted-pair, G.hn over coax, 1G and 2.5G Ethernet over Cat-5e cable). On-board features: - 512 MiB DDR3 - 2 x 2.5G SFP via HSGMII SERDES interface to the A3720 SoC - USB 2.0 Type-C connector - 4GB eMMC - ETSI TS 101548 reverse powering via twisted pair (RJ45) or coax (F Type) Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Luis Torres <luis.torres@methode.com> Cc: Scott Roberts <scott.roberts@telus.com> Cc: Paul Arola <paul.arola@telus.com> Signed-off-by: Vladimir Vid <vladimir.vid@sartura.hr> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2019-02-05arm: mvebu: armada-xp-theadorable.dts: Enable PCIe DT nodesStefan Roese1-0/+14
Now that the PCIe driver supports DM and DT parsing, enable the PCIe DT nodes that are used by this board. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Dirk Eibach <dirk.eibach@gdsys.cc> Cc: Mario Six <mario.six@gdsys.cc> Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Cc: Phil Sutter <phil@nwl.cc> Cc: Marek Behún <marek.behun@nic.cz> Cc: VlaoMao <vlaomao@gmail.com>
2019-02-05arm: mvebu: armada-xp/37x.dtsi: Sync PCIe DT nodes with Linux v4.20Stefan Roese4-30/+56
This patch sync's the PCIe DT nodes with the recent Linux v4.20 version. This change makes it easier to reference specific PCIe nodes in the board dts files to e.g. enable a PCIe port as this is now necessary with the new DM PCI driver for these platforms. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Dirk Eibach <dirk.eibach@gdsys.cc> Cc: Mario Six <mario.six@gdsys.cc> Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Cc: Phil Sutter <phil@nwl.cc> Cc: Marek Behún <marek.behun@nic.cz> Cc: VlaoMao <vlaomao@gmail.com> Cc: Tom Rini <trini@konsulko.com>
2019-02-02Merge tag 'for-master-20190201' of git://git.denx.de/u-boot-rockchipTom Rini33-206/+4108
u-boot-rockchip changes for 2019.04-rc1: * support for Chromebook Bob * full pinctrl driver using DTS properties * documentation improvements * I2S support for some Rockchip SoCs
2019-02-02Merge tag 'mips-pull-2019-02-01' of git://git.denx.de/u-boot-mipsTom Rini3-0/+267
- MIPS: mscc: jr2: small fixes - MIPS: mscc: luton: add ethernet and switch driver - MIPS: mt76xx: fix timer frequency
2019-02-02Kconfig: Migrate CONFIG_BUILD_TARGETJagan Teki1-5/+0
Migrate CONFIG_BUILD_TARGET into Kconfig. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-02-01rockchip: rk3399: spl: ensure that debug_uart_init is calledPhilipp Tomsich1-2/+2
With the latest changes to add support for the Chromebook Bob, initialisation through debug_uart_init() did no longer get called for other targets. Fix this, by moving debug_uart_init() out of the Bob-specific Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01rockchip: Add support for chromebook_bobSimon Glass3-1/+51
Bob is a 10-inch chromebook produced by Asus. It has two USB 3.0 type-C ports, 4GB of SDRAM, WiFi and a 1280x800 display. It uses its USB ports for both power and external display. It includes a Chrome OS EC (Cortex-M3) to provide access to the keyboard and battery functions. Support so far includes only: - UART - SDRAM - MMC, SD card - Cros EC (but not keyboard) Not included: - Keyboard - Display - Sound - USB - TPM Bob is quite similar to Kevin, the Samsung Chromebook Plus, but support for this is not provided in this series. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01rockchip: gru: Add extra device-tree settingsSimon Glass3-4/+19
Add some U-Boot-specific settings. These should really go in the *u-boot.dtsi file, but it seems that rk3399 does not use that yet. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01rockchip: Implement spl_gpio in the GPIO driverSimon Glass1-0/+23
Allow rockchip boards to use GPIOs before driver model is ready. This is really only useful for setting GPIOs to enable the early debug console, if needed on some platforms. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01rockchip: Move pull-up/down enum into a common fileSimon Glass2-7/+7
At present this enum is only available to rk3288. Move it so that other rockchip SoCs can access it. It is needed for the SPL GPIO driver for rk3999 in a later patch. Also adjust the enum name to lower case. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01rockchip: Tidy up board include-file orderingSimon Glass7-13/+13
These board files have inconsistent #include ordering. Fix them. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01rockchip: Add settings for Samsung LPDDR3 4GB SDRAM 1866MHzSimon Glass1-0/+1542
This memory is used on Bob. Add settings for this, taken from coreboot. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01rockchip: Allow booting from SPISimon Glass1-0/+3
The u-boot,spl-boot-device property only allows MMC at present. Add SPI as well for boards that boot from SPI flash. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01rockchip: Adjust rk3399 device tree to be closer to linuxSimon Glass1-61/+371
This file has changed upstream, with some additions and changes. Move the U-Boot version towards this. Some USB changes seem to be incompatible with how the bindings work on rockchip in U-Boot. Testing is needed to make sure that USB still works correct, and adjust the code (not device tree) if not. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01rockchip: Bring in device tree files for rk3399-gruSimon Glass5-0/+1757
Bring in these files from Linux v4.20. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01ARM: dts: rk322x: Correct the uart2 default pin configurationDavid Wu1-2/+9
To match the iomux setting of uart2 at SPL, correct the uart2 default pin configuration, if not changed, the evb-rk3229 can't output the log message. Signed-off-by: David Wu <david.wu@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
generated by cgit v1.2.3 (git 2.39.0) at 2024-08-07 07:55:14 +0300