summaryrefslogtreecommitdiff
path: root/board/google/chromebook_link
AgeCommit message (Collapse)AuthorFilesLines
2020-09-01x86: Introduce USE_EARLY_BOARD_INIT optionAndy Shevchenko1-0/+1
Introduce USE_EARLY_BOARD_INIT option and select it by the actual users. Cc: George McCollister <george.mccollister@gmail.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-05-07SPDX: Convert all of our single license tags to Linux Kernel styleTom Rini2-5/+2
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2017-08-01x86: kconfig: Let board select SPI flashBin Meng1-0/+1
Only a specific type of SPI flash exists on a board, having board Kconfig to select the SPI flash seems to make more sense. Other flash types are not necessary except coreboot, which implies all available flash drivers there. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-01x86: kconfig: Select ARCH_EARLY_INIT_R in the platform KconfigBin Meng1-11/+0
This is architecture-dependent early initialization hence should be put in the platform Kconfig. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-01x86: kconfig: Let board select BOARD_EARLY_INIT_FBin Meng1-5/+0
CONFIG_BOARD_EARLY_INIT_F literally indicates board-specific codes and should be not 'default y' for all x86 boards. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-02-07x86: link: Add a config for 64-bit U-BootSimon Glass2-1/+8
Add a new board config which uses 64-bit U-Boot. This is not fully functional but is it a start. Missing features: - SDRAM sizing - Booting linux - EFI support - SCSI device init (and others) Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-02-07x86: link: Add a text base for 64-bit U-BootSimon Glass1-1/+2
Set up the 64-bit U-Boot text base if building for that target. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: Drop all the old pin configuration codeSimon Glass1-138/+0
We don't need this anymore - we can use device tree and the new pinconfig driver instead. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24x86: ivybridge: Move northbridge and PCH init into driversSimon Glass1-8/+0
Instead of calling the northbridge and PCH init from bd82x6x_init_extra() when the PCI bus is probed, call it from the respective drivers. Also drop the Northbridge init as it has no effect. The registers it touches appear to be read-only. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-13x86: ivybridge: Do not require HAVE_INTEL_MEBin Meng1-0/+1
Do not set HAVE_INTEL_ME by default as for some cases Intel ME firmware even does not reside on the same SPI flash as U-Boot. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2015-12-09x86: Remove HAVE_ACPI_RESUMEBin Meng1-1/+0
These are currently dead codes. Until we have complete ACPI support, we don't know if it works or not. Remove to avoid confusion. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2015-12-09x86: Remove CPU_INTEL_SOCKET_RPGA989Bin Meng1-1/+0
This Kconfig option name indicates it has something to do with cpu socket, however it is actually not the case. Remove it and move options inside it to NORTHBRIDGE_INTEL_IVYBRIDGE. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2015-12-09x86: Clean up ivybridge/chrome Kconfig optionsBin Meng1-1/+0
There are some options which are never used, and also some options which are selected by others but have never been a Kconfg option. Clean these up. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2015-07-15x86: Remove MARK_GRAPHICS_MEM_WRCOMBBin Meng1-1/+0
MARK_GRAPHICS_MEM_WRCOMB is not referenced anywhere in the code, hence remove it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-04-30x86: Kconfig: Remove deprecated CONFIG_SYS_EXTRA_OPTIONSBin Meng1-0/+3
Currently all x86 boards still use CONFIG_SYS_EXTRA_OPTIONS to define the text base address. Since it is deprecated, just remove it and use CONFIG_SYS_TEXT_BASE directly. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-04-18x86: cros_ec: Drop unnecessary initSimon Glass1-3/+0
Since driver model will probe the EC when it is first used, we do not need to init it explicitly. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-18dm: x86: pci: Convert coreboot to use driver model for pciSimon Glass1-0/+9
Move coreboot-x86 over to driver model for PCI. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-02-06x86: Rename MMCONF_BASE_ADDRESS and make it common across x86Simon Glass1-2/+1
This setting will be used by more than just ivybridge so make it common. Also rename it to PCIE_ECAM_BASE which is a more descriptive name. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-01-13x86: Move CONFIG_SYS_CAR_xxx to KconfigBin Meng1-0/+8
Move CONFIG_SYS_CAR_ADDR and CONFIG_SYS_CAR_SIZE to Kconfig so that we don't need them in the board configuration file thus the same board configuratoin file can be used to build both coreboot version and bare version. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-01-13x86: Move CONFIG_X86_RESET_VECTOR and CONFIG_SYS_X86_START16 to KconfigBin Meng1-0/+1
Convert CONFIG_X86_RESET_VECTOR and CONFIG_SYS_X86_START16 to Kconfig options so that we can remove them from board configuration file. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2014-12-19x86: ich6-gpio: Add Intel Tunnel Creek GPIO supportBin Meng1-1/+1
Intel Tunnel Creek GPIO register block is compatible with current ich6-gpio driver, except the offset and content of GPIO block base address register in the LPC PCI configuration space are different. Use u16 instead of u32 to store the 16-bit I/O address of the GPIO registers so that it could support both Ivybridge and Tunnel Creek. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2014-12-14x86: ich6-gpio: Move setup_pch_gpios() to board support codesBin Meng1-0/+40
Movie setup_pch_gpios() in the ich6-gpio driver to the board support codes, so that the driver does not need to know any platform specific stuff (ie: include the platform specifc chipset header file). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2014-12-14x86: Make ROM_SIZE configurable in KconfigBin Meng1-0/+1
Currently the ROM_SIZE is hardcoded to 8MB in arch/x86/Kconfig. This will not be the case when adding additional board support. Hence we make ROM_SIZE configurable (512KB/1MB/2MB/4MB/8MB/16MB) and have the board Kconfig file select the default ROM_SIZE. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2014-11-25x86: chromebook_link: Enable the Chrome OS ECSimon Glass1-0/+4
Enable the Chrome OS EC so that it can be used from U-Boot. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25x86: Remove board_early_init_r()Simon Glass1-5/+0
This function is not needed. Remove it to improve the generic init sequence slightly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-21x86: chromebook_link: Enable GPIO supportSimon Glass1-0/+107
Enable GPIO support and provide the required GPIO setup information to the driver. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21x86: chromebook_link: Implement CAR support (cache as RAM)Simon Glass1-0/+12
Add support for CAR so that we have memory to use prior to DRAM init. On link there is a total of 128KB of CAR available, although some is used for the memory reference code. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21x86: Emit post codes in startup code for ChromebooksSimon Glass1-0/+4
On x86 it is common to use 'post codes' which are 8-bit hex values emitted from the code and visible to the user. Traditionally two 7-segment displays were made available on the motherboard to show the last post code that was emitted. This allows diagnosis of a boot problem since it is possible to see where the code got to before it died. On modern hardware these codes are not normally visible. On Chromebooks they are displayed by the Embedded Controller (EC), so it is useful to emit them. We must enable this feature for the EC to see the codes, so add an option for this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-21x86: Add chromebook_link boardSimon Glass4-0/+53
This board is a 'bare' version of the existing 'link 'board. It does not require coreboot to run, but is intended to start directly from the reset vector. This initial commit has place holders for a wide range of features. These will be added in follow-on patches and series. So far it cannot be booted as there is no ROM image produced, but it does build without errors. Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.2.3 (git 2.39.0) at 2024-08-10 20:55:46 +0300