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2023-07-22am62a: dts: binman: Package tiboot3.bin, tispl.bin, u-boot.imgNeha Malcom Francis1-0/+2
Support added for HS-SE, HS-FS and GP boot binaries for AM62ax. HS-SE: * tiboot3-am62ax-hs-evm.bin * tispl.bin * u-boot.img HS-FS: * tiboot3-am62ax-hs-fs-evm.bin * tispl.bin * u-boot.img GP: * tiboot3.bin --> tiboot3-am62ax-gp-evm.bin * tispl.bin_unsigned * u-boot.img_unsigned It is to be noted that the bootflow followed by AM62ax requires: tiboot3.bin: * R5 SPL * R5 SPL dtbs * TIFS * board-cfg * pm-cfg * sec-cfg * rm-cfg tispl.bin: * DM * ATF * OP-TEE * A72 SPL * A72 SPL dtbs u-boot.img: * A72 U-Boot * A72 U-Boot dtbs Reviewed-by: Simon Glass <sjg@chromium.org> [afd@ti.com: changed output binary names appropriately] Signed-off-by: Andrew Davis <afd@ti.com> Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
2023-07-22am62a: yaml: Add board configs for AM62axNeha Malcom Francis5-0/+2589
Added YAML configs for AM62ax Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
2023-07-22am625: dts: binman: Package tiboot3.bin, tispl.bin and u-boot.imgNeha Malcom Francis1-0/+2
Support added for HS-SE, HS-FS and GP boot binaries for AM62. HS-SE: * tiboot3-am62x-hs-evm.bin * tispl.bin * u-boot.img HS-FS: * tiboot3-am62x-hs-fs-evm.bin * tispl.bin * u-boot.img GP: * tiboot3.bin --> tiboot3-am62x-gp-evm.bin * tispl.bin_unsigned * u-boot.img_unsigned It is to be noted that the bootflow followed by AM62 requires: tiboot3.bin: * R5 SPL * R5 SPL dtbs * TIFS * board-cfg * pm-cfg * sec-cfg * rm-cfg tispl.bin: * DM * ATF * OP-TEE * A72 SPL * A72 SPL dtbs u-boot.img: * A72 U-Boot * A72 U-Boot dtbs Reviewed-by: Simon Glass <sjg@chromium.org> [afd@ti.com: changed output binary names appropriately] Signed-off-by: Andrew Davis <afd@ti.com> Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
2023-07-22am62: yaml: Add board configs for AM62Neha Malcom Francis4-0/+1515
Added YAML configs for AM62 Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
2023-07-22j721s2: dts: binman: Package tiboot3.bin, tispl.bin and u-boot.imgNeha Malcom Francis1-0/+2
Support has been added for both HS-SE, HS-FS and GP images. HS-SE: * tiboot3-j721s2-hs-evm.bin * tispl.bin * u-boot.img HS-FS: * tiboot3-j721s2-hs-fs-evm.bin * tispl.bin * u-boot.img GP: * tiboot3.bin --> tiboot3-j721s2-gp-evm.bin * tispl.bin_unsigned * u-boot.img_unsigned It is to be noted that the bootflow followed by J721S2 requires: tiboot3.bin: * R5 SPL * R5 SPL dtbs * TIFS * board-cfg * pm-cfg * sec-cfg * rm-cfg tispl.bin: * DM * ATF * OP-TEE * A72 SPL * A72 SPL dtbs u-boot.img: * A72 U-Boot * A72 U-Boot dtbs Reviewed-by: Simon Glass <sjg@chromium.org> [afd@ti.com: changed output binary names appropriately] Signed-off-by: Andrew Davis <afd@ti.com> Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
2023-07-22j721s2: yaml: Add board configs for J721S2Neha Malcom Francis4-0/+3328
Added YAML configs for J721S2 Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
2023-07-22am64x: dts: binman: Package tiboot3.bin, tispl.bin u-boot.imgNeha Malcom Francis1-0/+2
Support added for HS and GP boot binaries for AM64x. HS-SE: * tiboot3-am64x_sr2-hs-evm.bin * tispl.bin * u-boot.img HS-FS: * tiboot3-am64x_sr2-hs-fs-evm.bin * tispl.bin * u-boot.img GP: * tiboot3.bin --> tiboot3-am64x-gp-evm.bin * tispl.bin_unsigned * u-boot.img_unsigned Note that the bootflow followed by AM64x requires: tiboot3.bin: * R5 SPL * R5 SPL dtbs * sysfw * board-cfg * pm-cfg * sec-cfg * rm-cfg tispl.bin: * ATF * OP-TEE * A53 SPL * A53 SPL dtbs u-boot.img: * A53 U-Boot * A53 U-Boot dtbs Reviewed-by: Simon Glass <sjg@chromium.org> [afd@ti.com: changed output binary names appropriately] Signed-off-by: Andrew Davis <afd@ti.com> Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
2023-07-22am64x: yaml: Add board configs for AM64xNeha Malcom Francis4-0/+1828
Added YAML configs for AM64xx Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
2023-07-22am65: dts: binman: Package tiboot3.bin, sysfw.itb, tispl.bin, u-boot.imgNeha Malcom Francis1-0/+2
Support has been added for both HS-SE(SR 2.0) and GP(SR 2.0) images. HS-SE: * tiboot3-am65x_sr2-hs-evm.bin * sysfw-am65x_sr2-hs-evm.itb * tispl.bin * u-boot.img GP: * tiboot3.bin --> tiboot3-am65x_sr2-gp-evm.bin * sysfw.itb --> sysfw-am65x_sr2-gp-evm.itb * tispl.bin_unsigned * u-boot.img_unsigned Note that the bootflow followed by AM65x requires: tiboot3.bin: * R5 SPL * R5 SPL dtbs sysfw.itb: * sysfw * board-cfg * pm-cfg * sec-cfg * rm-cfg tispl.bin: * ATF * OP-TEE * A53 SPL * A53 SPL dtbs u-boot.img: * A53 U-Boot * A53 U-Boot dtbs Reviewed-by: Simon Glass <sjg@chromium.org> [afd@ti.com: changed output binary names appropriately] Signed-off-by: Andrew Davis <afd@ti.com> Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
2023-07-22am65x: yaml: Add AM65x board config filesNeha Malcom Francis4-0/+2495
Added YAML configs for AM65x Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
2023-07-22j7200: dts: binman: Package tiboot3.bin, tispl.bin, u-boot.imgNeha Malcom Francis1-0/+2
Support has been added for both HS-SE(SR 2.0), HS-FS(SR 2.0) and GP images. HS-SE: * tiboot3-j7200_sr2-hs-evm.bin * tispl.bin * u-boot.img HS-FS: * tiboot3-j7200_sr2-hs-fs-evm.bin * tispl.bin * u-boot.img GP: * tiboot3.bin --> tiboot3-j7200-gp-evm.bin * tispl.bin_unsigned * u-boot.img_unsigned It is to be noted that the bootflow followed by J7200 requires: tiboot3.bin: * R5 SPL * R5 SPL dtbs * TIFS * board-cfg * pm-cfg * sec-cfg * rm-cfg tispl.bin: * DM * ATF * OP-TEE * A72 SPL * A72 SPL dtbs u-boot.img: * A72 U-Boot * A72 U-Boot dtbs Reviewed-by: Simon Glass <sjg@chromium.org> [afd@ti.com: changed output binary names appropriately] Signed-off-by: Andrew Davis <afd@ti.com> Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
2023-07-22j7200: yaml: Add J7200 board config filesNeha Malcom Francis4-0/+2493
Added YAML configs for J7200 Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
2023-07-22j721e: dts: binman: Package tiboot3.bin, sysfw.itb, tispl.bin, u-boot.imgNeha Malcom Francis1-0/+2
By providing entries in the binman node of the device tree, binman will be able to find and package board config artifacts generated by TIBoardConfig with sysfw.bin and generate the final image sysfw.itb. It will also pick out the R5 SPL and sign it with the help of TI signing entry and generate the final tiboot3.bin. Entries for A72 build have been added to k3-j721e-binman.dtsi to generate tispl.bin and u-boot.img. Support has been added for both HS-SE(SR 1.1), HS-FS(SR 2.0) and GP images In HS-SE, the encrypted system firmware binary must be signed along with the signed certificate binary. HS-SE: * tiboot3-j721e_sr1_1-hs-evm.bin * sysfw-j721e_sr1_1-hs-evm.itb * tispl.bin * u-boot.img HS-FS: * tiboot3-j721e_sr2-hs-fs-evm.bin * sysfw-j721e_sr2-hs-fs-evm.itb * tispl.bin * u-boot.img GP: * tiboot3.bin -->tiboot3-j721e-gp-evm.bin * sysfw.itb --> sysfw-j721e-gp-evm.itb * tispl.bin_unsigned * u-boot.img_unsigned It is to be noted that the bootflow followed by J721E requires: tiboot3.bin: * R5 SPL * R5 SPL dtbs sysfw.itb: * TIFS * board-cfg * pm-cfg * sec-cfg * rm-cfg tispl.bin: * DM * ATF * OP-TEE * A72 SPL * A72 SPL dtbs u-boot.img: * A72 U-Boot * A72 U-Boot dtbs Reviewed-by: Simon Glass <sjg@chromium.org> [afd@ti.com: changed output binary names appropriately] Signed-off-by: Andrew Davis <afd@ti.com> Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
2023-07-22j721e: schema: yaml: Add general schema and J721E board config filesNeha Malcom Francis5-0/+4038
Schema file in YAML must be provided in board/ti/common for validating input config files and packaging system firmware. The schema includes entries for rm-cfg, board-cfg, pm-cfg and sec-cfg. Board config files must be provided in board/ti/<devicename> in YAML. These can then be consumed for generation of binaries to package system firmware. Added YAML configs for J721E in particular. Signed-off-by: Tarun Sahu <t-sahu@ti.com> [n-francis@ti.com: prepared patch for upstreaming] Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
2023-07-22binman: ti-secure: Add support for TI signingNeha Malcom Francis2-0/+61
The ti-secure entry contains certificate for binaries that will be loaded or booted by system firmware whereas the ti-secure-rom entry contains certificate for binaries that will be booted by ROM. Support for both these types of certificates is necessary for booting of K3 devices. Reviewed-by: Simon Glass <sjg@chromium.org> [vigneshr@ti.com: fixed inconsist cert generation by multiple packing] Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
2023-07-21board: ti: am62x: evm: Update function calls for splash screenNikhil M Jain1-26/+15
Use spl_dcache_enable, in place of setup_dram, arch_reserve_mmu to set up pagetable, initialise DRAM and enable Dcache to avoid multiple function calls. Check for CONFIG_SPL_VIDEO in place of CONFIG_SPL_VIDEO_TIDSS to prevent any build failure in case video config is not defined and video related functions are called. Check for CONFIG_SPL_SPLASH_SCREEN and CONFIG_SPL_BMP before calling splash_display to avoid compilation failure. Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
2023-07-21board: ti: am62x: evm: Include necessary header filesNikhil M Jain1-0/+1
At the time of compilation evm.c gives below warning for implicit declaration of enable_caches, to mitigate this include cpu_func.h. board/ti/am62x/evm.c: In function ‘spl_board_init’: board/ti/am62x/evm.c:90:9: warning: implicit declaration of function ‘enable_caches’ [-Wimplicit-function-declaration] 90 | enable_caches(); Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
2023-07-21arm64: zynqmp: Switch to amd.com emailsMichal Simek10-10/+10
Update my and DPs email address to match current setup. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/aba5b19b9c5a95608829e86ad5cc4671c940f1bb.1688992543.git.michal.simek@amd.com
2023-07-21arm64: versal-net: spi: Update boot sequence dynamicallyAshok Reddy Soma1-3/+21
Currently xspi0 is used for all spi boot modes, it means it will use "sf probe 0 0 0" for all spi's irrespective of which node it is wired. Get boot sequence from dev_seq() and update boot command for xspi dynamically. As a result bootcmd for spi is updated as below when two instances of spi are present in DT node. bootcmd_xspi0=devnum_xspi=0; run xspi_boot bootcmd_xspi1=devnum_xspi=1; run xspi_boot xspi_boot=sf probe $devnum_xspi:0 0 0 && sf read $scriptaddr $script_offset_f $script_size_f && echo XSPI: Trying to boot script at ${scriptaddr} && source ${scriptaddr}; echo XSPI: SCRIPT FAILED: continuing...; Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Link: https://lore.kernel.org/r/20230614093058.30438-1-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-07-21xilinx: zynq: Add the missing function prototypesAlgapally Santosh Sagar1-0/+2
Add the missing prototypes for the functions pointed by the below sparse warnings warning: no previous prototype for 'set_dfu_alt_info' [-Wmissing-prototypes] warning: no previous prototype for 'board_debug_uart_init' [-Wmissing-prototypes] Signed-off-by: Algapally Santosh Sagar <santoshsagar.algapally@amd.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Link: https://lore.kernel.org/r/20230614090359.10809-7-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-07-21arm: zynq: Pass the missing argument type in function definitionAlgapally Santosh Sagar4-8/+8
Pass missing argument type in the function definition to fix the sparse warning, warning: old-style function definition [-Wold-style-definition] Signed-off-by: Algapally Santosh Sagar <santoshsagar.algapally@amd.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Link: https://lore.kernel.org/r/20230614090359.10809-6-ashok.reddy.soma@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-07-19Merge tag 'fsl-qoriq-2023-7-13' of ↵Tom Rini4-2/+46
https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq Enable DM_SERIAL for T2080RDB, T4240RDB, T1042D4RDB, T1024RDB
2023-07-17sandbox: Install ACPI tables on startupSimon Glass1-0/+16
With x86 we set up the ACPI tables on startup so they can be examined. Do the same with sandbox, so it is consistent. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-07-17sandbox: Correct header order in board fileSimon Glass1-3/+3
Fix the header order in this file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-07-17bios_emulator: Add Kconfig and adjust Makefile for SPLSimon Glass1-7/+0
The Kconfig for this is currently inside a particular board. Move it into the correct place and allow use in SPL, so that video can be used there if needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-07-14arch: arm: npcm8xx: add cpu version and 4G ram supportJim Liu1-3/+67
Add npcm8xx A2 cpu version check and add 4G RAM support Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2023-07-14board: nuvoton: arbel: change uboot load addressJim Liu1-2/+2
use new memory layout and change uboot load address. open tpm, tee and more config feature No need to reserve top memory because the reserved space is moved to the bottom area of memory. Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2023-07-14board: nuvoton: add env setting for boot to linuxJim Liu1-0/+7
add console and mem env to boot to linux kernel Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2023-07-14Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvellTom Rini4-1/+27
- mvebu: Thecus: Misc enhancement and cleanup (Tony) - mvebu: Add AC5X Allied Telesis x240 board support incl NAND controller enhancements for this SoC (Chris)
2023-07-14Merge tag 'u-boot-imx-20230713' of ↵Tom Rini35-872/+1780
https://gitlab.denx.de/u-boot/custodians/u-boot-imx u-boot-imx-20230713 ------------------- Merge for 2023.10. CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/16888
2023-07-13arm: mvebu: Add Allied Telesis x240 boardChris Packham3-0/+26
The x240 and SE240 are a series of L2+ switches from Allied Telesis. There are a number of them in the range but as far as U-Boot is concerned all the CPU block components are the same so there's only one board defined. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
2023-07-13mx7dsabresd: Retrieve the second MAC address from fusesFabio Estevam1-0/+6
Currently, a random MAC address is assigned to eth1 in Linux. Fix this behavor by retrieving the second MAC address from the fuses. Signed-off-by: Fabio Estevam <festevam@denx.de>
2023-07-13verdin-imx8mm/verdin-imx8mp: synchronise device trees with linuxMarcel Ziswiler2-2/+0
Synchronise device trees with linux v6.5-rc1. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2023-07-13board: colibri-imx8x: initialize snvsAndrejs Cainikovs1-0/+8
Initialize Secure Non-Volatile Storage, aka SNVS. Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
2023-07-13imx8mn-var-som: adjust PHY reset gpios according to hardware configurationHugo Villeneuve1-0/+80
For SOM with the EC configuration, the ethernet PHY is located on the SOM itself, and connected to the CPU ethernet controller. It has a reset line controlled via GPIO1_IO9. In this configuration, the PHY located on the carrier board is not connected to anything and is therefore not used. For SOM without EC configuration, the ethernet PHY on the carrier board is connected to the CPU ethernet controller. It has a reset line controlled via the GPIO expander PCA9534_IO5. The hardware configuration (EC) is determined at runtime by reading from the SOM EEPROM. To support both hardware configurations (EC and non-EC), adjust/fix the PHY reset gpios according to the hardware configuration read at runtime from the SOM EEPROM. This adjustement is done in U-Boot (OF_BOARD_FIXUP) and kernel (OF_BOARD_SETUP) device trees. Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
2023-07-13ARM: dts: imx: Fix eMMC boot on Data Modul i.MX8M Plus eDM SBCMarek Vasut1-0/+14
In case the i.MX8M Plus starts from eMMC BOOT1/BOOT2 HW partitions, the flash.bin container is stored at offset 0 from the start, that means the fitImage itb is at offset 0x2c0 instead of 0x300 sectors from the start. Handle this difference in custom spl_mmc_get_uboot_raw_sector() . Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2023-07-13configs: imx8m: Prepare imx8m-venice boards for HAB supportTim Harvey1-0/+5
In order to enable HAB, FSL_CAAM, ARCH_MISC_INIT and SPL_CRYPTO should be enabled in Kconfig like other i.MX8M boards. This also needs to occur in the SPL so enable CONFIG_SPL_BOARD_INIT and add a void spl_board_init function which calls arch_misc_init to probe the CAAM driver. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-07-13board: gateworks: venice: switch to 2-bank dram configTim Harvey1-1/+1
Switch to a 2-bank dram config to properly support 4GiB. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-07-13board: phytec: phycore_imx8mm: Update lpddr4_timingCem Tenruh1-744/+742
Update RAM Timings for 2GB RAM based on DDR Controller Configuration Spreadsheet revision 22. Including the update of the refresh rate to workaround errata ERR050805. Signed-off-by: Cem Tenruh <c.tenruh@phytec.de>
2023-07-13imx: bootaux: change names of MACROs used to boot MCU on iMX devicesPeng Fan4-4/+4
The current bootaux supports i.MX8M and i.MX93, but the name "_M4_" implies that the SoCs have Cortex-M4. Actually i.MX8MM/Q use Cortex-M4, i.MX8MN/P use Cortex-M7, i.MX93 use Cortex-M33, so use "_MCU_" in place of "_M4_" to simplify the naming. Signed-off-by: faqiang.zhu <faqiang.zhu@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13imx: imx8ulp: start the ELE RNG at bootPeng Fan1-0/+10
On the imx8ulp A1 SoC, the ELE RNG needs to be manually started. Signed-off-by: Clement Faure <clement.faure@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13imx: use generic name ele(EdgeLockSecure Enclave)Peng Fan2-6/+5
Per NXP requirement, we rename all the NXP EdgeLock Secure Enclave code including comment, folder and API name to ELE to align. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13imx: congatec/cgtqmx8: correct SCU API usagePeng Fan1-4/+4
The return value is int type, not sc_err_t(u8), correct the usage. Signed-off-by: Peng Fan <peng.fan@nxp.com> Tested-by: Oliver Graute <oliver.graute@kococonnector.com> Reviewed-by: Oliver Graute <oliver.graute@kococonnector.com>
2023-07-13imx: advantech: correct SCU API usagePeng Fan2-6/+6
The return value is int type, not sc_err_t(u8), correct the usage. Signed-off-by: Peng Fan <peng.fan@nxp.com> Tested-by: Oliver Graute <oliver.graute@kococonnector.com> Reviewed-by: Oliver Graute <oliver.graute@kococonnector.com>
2023-07-13imx: siemens/capricorn: correct SCU API usagePeng Fan1-6/+6
The return value is int type, not sc_err_t(u8), correct the usage. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13imx: toradex/colibri-imx8x: correct SCU API usagePeng Fan1-5/+5
The return value is int type, not sc_err_t(u8), correct the usage. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13imx: toradex/apalis-imx8: correct SCU API usagePeng Fan1-5/+5
The return value is int type, not sc_err_t(u8), correct the usage. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13colibri_imx6: fix RALAT and WALAT valuesStefan Eichenberger1-4/+2
Running a memtest in U-Boot and Linux shows that some Colibri iMX6 produce bitflips at temperatures above 60°C. This happens because the RALAT and WALAT values on the Colibri iMX6 are too low. The problems were introduced by commit 09dbac8174c4 ("mx6: ddr: Restore ralat/walat in write level calibration") before the calibration process overwrote the values and set them to the maximum value. With this commit, we make sure that the RALAT and WALAT values are set to the maximum values again. This has been proven to work for years. Fixes: 09dbac8174c4 ("mx6: ddr: Restore ralat/walat in write level calibration") Signed-off-by: Stefan Eichenberger <stefan.eichenberger@toradex.com> Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
2023-07-13board: freescale: t102xrdb: implement get_serial_clockCamelia Groza1-1/+9
The serial clock is provided by the get_serial_clock() callback on PPC under DM_SERIAL. Use the same method to compute the clock as for non-DM_SERIAL use cases. Signed-off-by: Camelia Groza <camelia.groza@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13board: freescale: t102xrdb: enumerate PCI devicesCamelia Groza1-0/+2
Call pci_init() to force PCI enumeration at probe time. Signed-off-by: Camelia Groza <camelia.groza@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
generated by cgit v1.2.3 (git 2.39.0) at 2024-09-20 02:46:55 +0300