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At this point, the remaining places where we have a symbol that is
defined as CONFIG_... are in fairly odd locations. While as much dead
code has been removed as possible, some of these locations are simply
less obvious at first. In other cases, this code is used, but was
defined in such a way as to have been missed by earlier checks. Perform
a rename of all such remaining symbols to be CFG_... rather than
CONFIG_...
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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Remove some CONFIG symbols and related comments, etc, that are unused
within the code itself at this point.
Signed-off-by: Tom Rini <trini@konsulko.com>
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The event framework is just that, a framework. Enabling it by itself
does nothing, so we shouldn't ask the user about it. Reword (and correct
typos) around this the option and help text. This also applies to
DM_EVENT and EVENT_DYNAMIC. Only EVENT_DEBUG and CMD_EVENT should be
visible to the user to select, when EVENT is selected.
With this, it's time to address the larger problems. When functionality
uses events, typically via EVENT_SPY, the appropriate framework then
must be select'd and NOT imply'd. As the functionality will cease to
work (and so, platforms will fail to boot) this is non-optional and
where select is appropriate. Audit the current users of EVENT_SPY to
have a more fine-grained approach to select'ing the framework where
used. Also ensure the current users of event_register and also select
EVENT_DYNAMIC.
Cc: AKASHI Takahiro <takahiro.akashi@linaro.org>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reported-by: Oliver Graute <Oliver.Graute@kococonnector.com>
Reported-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Fixes: 7fe32b3442f0 ("event: Convert arch_cpu_init_dm() to use events")
Fixes: 42fdcebf859f ("event: Convert misc_init_f() to use events")
Fixes: c5ef2025579e ("dm: fix DM_EVENT dependencies")
Signed-off-by: Tom Rini <trini@konsulko.com>
Tested-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Fabio Estevam <festevam@denx.de>
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The PX30-µQ7 (Ringneck) is a system-on-module featuring the Rockchip
PX30 in a micro Qseven-compatible form-factor.
PX30-µQ7 features:
* CPU: quad-core Cortex-A35
* DRAM: 2GB dual-channel
* eMMC: onboard eMMC
* SD/MMC
* TI DP83825I 10/100Mbps PHY
* USB:
* USB2.0 dual role port
* 3x USB2.0 host via onboard USB2.0 hub
* Display: MIPI-DSI
* Camera: MIPI-CSI
* onboard 2.4GHz WiFi + Bluetooth module
* Companion Controller: on-board additional microcontroller
(STM32 Cortex-M0 or ATtiny):
* RTC
* fan controller
* CAN (only STM32)
The non-U-Boot DTS files are imported from Linux v6.2-rc2.
Cc: Quentin Schulz <foss+uboot@0leil.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
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The Pinephone Pro is another device by PINE64. It's closely related
to the Pinebook Pro of which this initial support is derived from.
Specification:
- A variant of the Rockchip RK3399
- A 6 inch 720*1440 DSI display
- Front and rear cameras
- Type-C interface with alt mode display (DP 1.2) and PD charging
- 4GB LPDDR4 RAM
- 128GB eMMC
- mSD card slot
- An AP6255 module for 802.11ac WiFi and Bluetooth 5
- Quectel EG25-G 4G/LTE modem
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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Neural Compute Module 2(Neu2) IO board is an industrial form factor
IO board from Edgeble AI.
General features:
- microSD slot
- MIPI DSI connector
- 2x USB Host
- 1x USB OTG
- Ethernet
- mini PCIe
- Onboard PoE
- RS485, RS232, CAN
- Micro Phone array
- Speaker
- RTC battery slot
- 40-pin expansion
Neu2 needs to mount on top of this IO board in order to create complete
Edgeble Neural Compute Module 2(Neu2) IO platform.
Add support for it.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
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We have common ddr types in rockchip or in general. So use
the common ddr type names instead of per Rockchip SoC to
avoid confusion.
The respective ddr type names will use on the associated
ddr SoC driver as these drivers are built per SoC at a time.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
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Add board identifiers for STMicroelectronics STM32MP13x boards:
- DISCO board: MB1635
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
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When OP-TEE is used, the SMC for BSEC management are not available and
the STM32MP BSEC pseudo TA must be used (it is mandatory for STM32MP13
and it is a new feature for STM32MP15x).
The BSEC driver try to open a session to this PTA BSEC at probe
and use it for OTP read or write access to fuse or to shadow.
This patch also adapts the commands stm32key and stboard to handle
the BSEC_LOCK_PERM lock value instead of 1.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
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Before this was named just evm, which doesn't match the naming
of the other TI board file directory and makes it look like a
common directory for evms. Name this omap3evm.
Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Derald Woods <woods.technical@gmail.com>
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https://source.denx.de/u-boot/custodians/u-boot-at91 into next
First set of u-boot-at91 features for the 2023.04 cycle:
This feature set includes the new DM-based NAND flash driver (old non-DM
driver is still kept for backwards compatibility), and the move to DM
NAND flash driver for sam9x60ek board. Feature set also includes
devicetree alignment for sama7g5 with Linux, devicetree alignment on USB
with Linux for all boards (sama5, sam9x60), chip id for sama7g5, minor
configs and tweaks.
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Add new config for storing environment from SDMMC1.
Signed-off-by: Mihai Sain <mihai.sain@microchip.com>
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Set blue led on at boot time in order to highlight that u-boot is loaded.
This is done for all sam9x60 based boards which contain an RGB led.
Signed-off-by: Mihai Sain <mihai.sain@microchip.com>
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EEPROM detection logic in ti_i2c_eeprom_get() involves figuring out
whether addressing is 1-byte or 2-byte. There are currently different
behaviours seen across boards as documented in commit bf6376642fe8
("board: ti: common: board_detect: Fix EEPROM read quirk"). Adding to
the list, we see that there are 2-byte EEPROMs that read properly
with 1-byte addressing with no offset.
For ti_i2c_eeprom_am6_get where eeprom parse operation is dynamic, the
earlier commit d2ab2a2bafd5 ("board: ti: common: board_detect: Fix
EEPROM read quirk for AM6 style data") tried to resolve this by running
ti_i2c_eeprom_get() twice. However this commit along with its former
commit fails on J7 platforms where EEPROM successfully return back the
header on 1-byte addressing and continues to do so until an offset is
introduced. So the second read incorrectly determines the EEPROM as
1-byte addressing.
A more generic solution is introduced here to solve
this issue: 1-byte read without offset and 1-byte read with offset. If
both passes, it follows 1-byte addressing else we proceed with 2-byte
addressing check.
Tested on J721E, J7200, DRA7xx, AM64x
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Fixes: d2ab2a2bafd5 (board: ti: common: board_detect: Fix EEPROM read quirk for AM6 style data)
Fixes: bf6376642fe8 (board: ti: common: board_detect: Fix EEPROM read quirk)
Tested-By: Matwey V. Kornilov <matwey.kornilov@gmail.com>
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At this point in the conversion there should be no need to have logic to
disable some symbol during the SPL build as all symbols should have an
SPL counterpart.
The main real changes done here are that we now must make proper use of
CONFIG_IS_ENABLED(DM_SERIAL) rather than many of the odd tricks we
developed prior to CONFIG_IS_ENABLED() being available.
Signed-off-by: Tom Rini <trini@konsulko.com>
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Rename the CONFIG_POWER_BD71837_I2C_* symbols to not have the CONFIG
prefix and be local to the file they are used in.
Signed-off-by: Tom Rini <trini@konsulko.com>
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Perform simple renames of:
CONFIG_VSC7385_IMAGE to CFG_VSC7385_IMAGE
CONFIG_VSC7385_IMAGE_SIZE to CFG_VSC7385_IMAGE_SIZE
Signed-off-by: Tom Rini <trini@konsulko.com>
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Perform a simple rename of CONFIG_TESTPIN_REG to CFG_TESTPIN_REG
Signed-off-by: Tom Rini <trini@konsulko.com>
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Perform a simple rename of CONFIG_TESTPIN_MASK to CFG_TESTPIN_MASK
Signed-off-by: Tom Rini <trini@konsulko.com>
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Perform a simple rename of CONFIG_SMP_PEN_ADDR to CFG_SMP_PEN_ADDR
Signed-off-by: Tom Rini <trini@konsulko.com>
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Perform a simple rename of CONFIG_SLIC to CFG_SLIC
Signed-off-by: Tom Rini <trini@konsulko.com>
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Perform a simple rename of CONFIG_SET_DFU_ALT_BUF_LEN to CFG_SET_DFU_ALT_BUF_LEN
Signed-off-by: Tom Rini <trini@konsulko.com>
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Perform a simple rename of CONFIG_RESET_VECTOR_ADDRESS to CFG_RESET_VECTOR_ADDRESS
Signed-off-by: Tom Rini <trini@konsulko.com>
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Perform a simple rename of CONFIG_POWER_PFUZE100_I2C_ADDR to CFG_POWER_PFUZE100_I2C_ADDR
Signed-off-by: Tom Rini <trini@konsulko.com>
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Perform a simple rename of CONFIG_POWER_LTC3676_I2C_ADDR to CFG_POWER_LTC3676_I2C_ADDR
Signed-off-by: Tom Rini <trini@konsulko.com>
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Perform a simple rename of CONFIG_PL011_CLOCK to CFG_PL011_CLOCK
Signed-off-by: Tom Rini <trini@konsulko.com>
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Perform a simple rename of CONFIG_PHY_ID to CFG_PHY_ID
Signed-off-by: Tom Rini <trini@konsulko.com>
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Perform a simple rename of CONFIG_ODROID_REV_AIN to CFG_ODROID_REV_AIN
Signed-off-by: Tom Rini <trini@konsulko.com>
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Perform a simple rename of CONFIG_MXC_UART_BASE to CFG_MXC_UART_BASE
Signed-off-by: Tom Rini <trini@konsulko.com>
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Perform a simple rename of CONFIG_MAX_RAM_BANK_SIZE to CFG_MAX_RAM_BANK_SIZE
Signed-off-by: Tom Rini <trini@konsulko.com>
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Perform a simple rename of CONFIG_MAX_MEM_MAPPED to CFG_MAX_MEM_MAPPED
Signed-off-by: Tom Rini <trini@konsulko.com>
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Perform a simple rename of CONFIG_ICS307_REFCLK_HZ to CFG_ICS307_REFCLK_HZ
Signed-off-by: Tom Rini <trini@konsulko.com>
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Perform a simple rename of CONFIG_FSL_SERDES2 to CFG_FSL_SERDES2
Signed-off-by: Tom Rini <trini@konsulko.com>
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Perform a simple rename of CONFIG_FSL_SERDES1 to CFG_FSL_SERDES1
Signed-off-by: Tom Rini <trini@konsulko.com>
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Perform a simple rename of CONFIG_FSL_PMIC_BUS to CFG_FSL_PMIC_BUS
Signed-off-by: Tom Rini <trini@konsulko.com>
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Perform a simple rename of CONFIG_FEC_MXC_PHYADDR to CFG_FEC_MXC_PHYADDR
Signed-off-by: Tom Rini <trini@konsulko.com>
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Perform a simple rename of CONFIG_FEC_ENET_DEV to CFG_FEC_ENET_DEV
Signed-off-by: Tom Rini <trini@konsulko.com>
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Perform a simple rename of CONFIG_ETHBASE to CFG_ETHBASE
Signed-off-by: Tom Rini <trini@konsulko.com>
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Perform a simple rename of CONFIG_ET1100_BASE to CFG_ET1100_BASE
Signed-off-by: Tom Rini <trini@konsulko.com>
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Perform a simple rename of CONFIG_ENV_TOTAL_SIZE to CFG_ENV_TOTAL_SIZE
Signed-off-by: Tom Rini <trini@konsulko.com>
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Perform a simple rename of CONFIG_ENV_SROM_BANK to CFG_ENV_SROM_BANK
Signed-off-by: Tom Rini <trini@konsulko.com>
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Perform simple renames of:
CONFIG_DFU_ALT to CFG_DFU_ALT
CONFIG_DFU_ALT_BOOT_EMMC to CFG_DFU_ALT_BOOT_EMMC
CONFIG_DFU_ALT_BOOT_SD to CFG_DFU_ALT_BOOT_SD
CONFIG_DFU_ALT_SYSTEM to CFG_DFU_ALT_SYSTEM
CONFIG_DFU_ENV_SETTINGS to CFG_DFU_ENV_SETTINGS
Signed-off-by: Tom Rini <trini@konsulko.com>
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The way that the timer support is currently done for exynos/nexell
platforms relies on the legacy PWM infrastructure, and that needs to be
updated. However, we really cannot safely undef CONFIG_DM_PWM to build
the timer.c file without warnings. For now, rename the relevant legacy
functions to be prefixed with s5p_ and add prototypes to the arch pwm.h
files.
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Dzmitry Sankouski <dsankouski@gmail.com>
Cc: Stefan Bosch <stefan_b@posteo.net>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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At this point only the TARGET_T1042D4RDB variant of this is supported in
tree, so remove the remaining parts of the other platforms.
Signed-off-by: Tom Rini <trini@konsulko.com>
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This is always defined to 16K, so we move this over to
include/fsl_validate.h to start with. Next, we rename this from CONFIG_
to FSL_. Coalesce the various comments around this definition to be in
fsl_validate.h as well to explain the usage.
Signed-off-by: Tom Rini <trini@konsulko.com>
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No platforms enable this driver as there's no T1040D4RDB nor T1040RDB
support at this time. Remove.
Signed-off-by: Tom Rini <trini@konsulko.com>
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Enable this in the board Kconfig file, but then check for it via
CONFIG_IS_ENABLED so that it will only be true in the non-SPL case, as
is done today. As part of this we move some defines local to where
they are used as it's board specific.
Cc: Samuel Egli <samuel.egli@siemens.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
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This converts the following to Kconfig:
CONFIG_MONITOR_IS_IN_RAM
As part of this, reword some of the documentation slightly to reflect
that this is in Kconfig and not a define now.
Signed-off-by: Tom Rini <trini@konsulko.com>
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This removes the following unreferenced CONFIG symbols:
CONFIG_FDTADDR
CONFIG_FDTFILE
CONFIG_FLASH_SECTOR_SIZE
CONFIG_FSL_CPLD
CONFIG_HDMI_ENCODER_I2C_ADDR
CONFIG_I2C_MVTWSI
CONFIG_I2C_RTC_ADDR
CONFIG_IRAM_END
CONFIG_IRAM_SIZE
CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE
CONFIG_L1_INIT_RAM
CONFIG_MACB_SEARCH_PHY
CONFIG_MIU_2BIT_21_7_INTERLEAVED
CONFIG_MTD_NAND_VERIFY_WRITE
CONFIG_MVGBE_PORTS
CONFIG_NETDEV
CONFIG_NUM_DSP_CPUS
CONFIG_PHY_BASE_ADR
CONFIG_PHY_INTERFACE_MODE
CONFIG_PSRAM_SCFG
CONFIG_RAMBOOT_SPIFLASH
CONFIG_RAMBOOT_TEXT_BASE
CONFIG_RD_LVL
CONFIG_ROCKCHIP_SDHCI_MAX_FREQ
CONFIG_SETUP_INITRD_TAG
CONFIG_SH_QSPI_BASE
CONFIG_SMDK5420
CONFIG_SOCRATES
CONFIG_SPI_ADDR
CONFIG_SPI_FLASH_QUAD
CONFIG_SPI_FLASH_SIZE
CONFIG_SPI_HALF_DUPLEX
CONFIG_SPI_N25Q256A_RESET
CONFIG_TEGRA_SLINK_CTRLS
CONFIG_TPM_TIS_BASE_ADDRESS
CONFIG_UBOOT_SECTOR_COUNT
CONFIG_UBOOT_SECTOR_START
CONFIG_VAR_SIZE_SPL
CONFIG_VERY_BIG_RAM
And also:
BL1_SIZE
PHY_NO
RESERVE_BLOCK_SIZE
Signed-off-by: Tom Rini <trini@konsulko.com>
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Following how g_dnl_bind_fixup is used on other platforms, rename the
unchanging defines used here to be prefixed with EXYNOS rather than
Samsung, and define them here.
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
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