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starfive-tech/u-boot.git
Fedora_JH7100_2021.04
Fedora_JH7100_2021.07
Fedora_JH7100_upstream
Fedora_JH7100_upstream_devel
JH7100_Multimedia_V0.1.0
JH7100_VisionFive_OH_dev
JH7100_VisionFive_devel
JH7100_starlight_multimedia
JH7100_upstream
JH7100_upstream_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_devel-v3.9.3
dubhe_fpga_dev_v2023.10
master
rtthread_AMP
visionfive_devel
StarFive Tech U-Boot for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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mpc8xxx
Age
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Author
Files
Lines
2009-09-08
ppc/85xx/86xx: Bug fix: call to puts in probecpu() moved to checkcpu().
Poonam Aggrwal
1
-6
/
+0
2009-09-08
ppc/85xx/86xx: Device tree fixup for number of cores
Poonam Aggrwal
2
-0
/
+56
2009-09-08
ppc/85xx,86xx: Handling Unknown SOC version
Poonam Aggrwal
1
-2
/
+3
2009-09-08
ppc/8xxx: Refactor code to determine if PCI is enabled & agent/host
Kumar Gala
2
-0
/
+226
2009-09-08
ppc/8xxx: Remove ddr_pd_cntl register since it doesn't exist
Kumar Gala
1
-23
/
+0
2009-08-29
85xx: Added single core members of FSL P1xx/P2xx processors series
Poonam Aggrwal
1
-2
/
+6
2009-08-29
85xx: Added P1020 Processor Support.
Poonam Aggrwal
1
-0
/
+2
2009-08-29
8xxx: Removed CONFIG_NUM_CPUS from 85xx/86xx
Poonam Aggrwal
1
-34
/
+59
2009-08-29
8xxx: Refactored common cpu specific code for 85xx/86xx into one file.
Poonam Aggrwal
2
-0
/
+131
2009-07-22
85xx, 86xx: Add common board_add_ram_info()
Peter Tyser
2
-41
/
+98
2009-07-02
fsl_ddr: Fix DDR3 calculation of rank density with 8GB or more
Timur Tabi
1
-1
/
+1
2009-06-12
fsl-ddr: Fix handling of >4G of memory when !CONFIG_PHYS_64BIT
Kumar Gala
7
-39
/
+41
2009-03-30
fsl-ddr: add the DDR3 SPD infrastructure
Dave Liu
5
-46
/
+754
2009-03-30
fsl-ddr: Fix two bugs in the ddr infrastructure
Dave Liu
1
-1
/
+4
2009-02-17
fsl-ddr: Allow system to boot if we have more than 4G of memory
Kumar Gala
1
-1
/
+1
2009-02-17
fsl-ddr: ignore memctl_intlv_ctl setting if only one DDR controller
Kumar Gala
1
-0
/
+4
2009-01-24
fsl-ddr: use the 1T timing as default configuration
Dave Liu
1
-1
/
+1
2009-01-24
fsl-ddr: make the self refresh idle threshold configurable
Dave Liu
1
-4
/
+8
2009-01-24
fsl-ddr: clean up the ddr code for DDR3 controller
Dave Liu
1
-11
/
+13
2009-01-24
fsl-ddr: update the bit mask for DDR3 controller
Dave Liu
1
-4
/
+8
2008-12-04
fsl ddr skip interleaving if not supported.
Ed Swarthout
2
-12
/
+17
2008-10-18
Add debug information for DDR controller registers
Haiying Wang
1
-0
/
+13
2008-10-18
Check DDR interleaving mode
Haiying Wang
2
-5
/
+112
2008-10-18
Pass dimm parameters to populate populate controller options
Haiying Wang
4
-87
/
+7
2008-10-18
Make DDR interleaving mode work correctly
Haiying Wang
2
-12
/
+54
2008-10-18
rename CFG_ macros to CONFIG_SYS
Jean-Christophe PLAGNIOL-VILLARD
1
-7
/
+7
2008-09-13
Coding style cleanup, update CHANGELOG
Wolfgang Denk
1
-15
/
+15
2008-09-07
Fix compiler warning in mpc8xxx ddr code
Kumar Gala
1
-2
/
+4
2008-08-27
FSL DDR: Add DDR2 DIMM paramter support
Kumar Gala
1
-0
/
+339
2008-08-27
FSL DDR: Add DDR1 DIMM paramter support
Kumar Gala
1
-0
/
+343
2008-08-27
FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code.
Kumar Gala
9
-0
/
+2418