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starfive-tech/u-boot.git
Fedora_JH7100_2021.04
Fedora_JH7100_2021.07
Fedora_JH7100_upstream
Fedora_JH7100_upstream_devel
JH7100_Multimedia_V0.1.0
JH7100_VisionFive_OH_dev
JH7100_VisionFive_devel
JH7100_starlight_multimedia
JH7100_upstream
JH7100_upstream_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_devel-v3.9.3
dubhe_fpga_dev_v2023.10
master
rtthread_AMP
visionfive_devel
StarFive Tech U-Boot for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
root
/
drivers
/
clk
/
aspeed
Age
Commit message (
Expand
)
Author
Files
Lines
2018-11-05
aspeed: ast2500: fix D2-PLL clock setting in RGMII mode
Cédric Le Goater
1
-0
/
+38
2018-11-05
aspeed: ast2500: fix missing break in D2PLL clock enablement
Cédric Le Goater
1
-0
/
+1
2018-10-28
drivers: cosmetic: Convert SPDX license tags to Linux Kernel style
Patrick Delaunay
1
-2
/
+1
2018-05-07
SPDX: Convert all of our single license tags to Linux Kernel style
Tom Rini
1
-2
/
+1
2017-06-01
dm: Rename dev_addr..() functions
Simon Glass
1
-1
/
+1
2017-05-08
aspeed: Refactor SCU to use consistent mask & shift
maxims@google.com
1
-20
/
+19
2017-05-08
aspeed: Add support for Clocks needed by MACs
maxims@google.com
1
-31
/
+234
2017-05-08
aspeed: Add P-Bus clock in ast2500 clock driver
maxims@google.com
1
-0
/
+11
2017-05-08
aspeed: Make SCU lock/unlock functions part of SCU API
maxims@google.com
1
-16
/
+2
2017-02-08
aspeed: ast2500: Fix H-PLL and M-PLL clock rate calculation
maxims@google.com
1
-2
/
+2
2017-01-28
aspeed: Add basic ast2500-specific drivers and configuration
maxims@google.com
2
-0
/
+272