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starfive-tech/u-boot.git
Fedora_JH7100_2021.04
Fedora_JH7100_2021.07
Fedora_JH7100_upstream
Fedora_JH7100_upstream_devel
JH7100_Multimedia_V0.1.0
JH7100_VisionFive_OH_dev
JH7100_VisionFive_devel
JH7100_starlight_multimedia
JH7100_upstream
JH7100_upstream_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_devel-v3.9.3
dubhe_fpga_dev_v2023.10
master
rtthread_AMP
visionfive_devel
StarFive Tech U-Boot for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
root
/
drivers
/
clk
/
renesas
/
r8a77970-cpg-mssr.c
Age
Commit message (
Expand
)
Author
Files
Lines
2023-02-02
clk: renesas: Add R8A77970 SD0H/SD0 clocks for SDHI
Hai Pham
1
-5
/
+0
2023-02-02
clk: renesas: Add and enable CPG reset driver
Marek Vasut
1
-9
/
+6
2021-05-21
clk: renesas: Make reset controller modemr register offset configurable
Marek Vasut
1
-0
/
+1
2021-05-21
clk: renesas: Synchronize R-Car Gen3 tables with Linux 5.12
Marek Vasut
1
-64
/
+68
2021-04-26
clk: renesas: Only ever access documented bits in clock driver teardown
Marek Vasut
1
-11
/
+11
2020-12-13
dm: treewide: Rename auto_alloc_size members to be shorter
Simon Glass
1
-1
/
+1
2020-05-19
common: Drop linux/bitops.h from common header
Simon Glass
1
-0
/
+1
2018-05-07
SPDX: Convert all of our single license tags to Linux Kernel style
Tom Rini
1
-2
/
+1
2018-01-25
clk: renesas: Split SMSTPCR and RMSTPCR tables
Marek Vasut
1
-6
/
+12
2018-01-25
clk: renesas: Pull Gen3 specific bits into separate header
Marek Vasut
1
-0
/
+1
2018-01-25
clk: renesas: Make PLL configurations per-SoC
Marek Vasut
1
-0
/
+39
2018-01-25
clk: renesas: Make clk_ids per-driver
Marek Vasut
1
-0
/
+38
2018-01-25
clk: renesas: Split RCar Gen3 driver
Marek Vasut
1
-0
/
+149