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path: root/drivers/clk/rockchip
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2020-07-22drivers: clk: rockchip: clk_rk3328: Add SPI supportJohannes Krottmayer1-0/+31
Add SPI support for the RK3328 clock driver Signed-off-by: Johannes Krottmayer <krjdev@gmail.com> Cc: Kever Yang <kever.yang@rock-chips.com> Cc: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-06-27rockchip: clk: rk3188: change APLL to safe 600MHzAlexander Kochetkov1-1/+2
The commit 84a6a27ae3ff ("rockchip: rk3188: init CPU freq in clock driver") changed ARM clock from 600MHz to 1600MHz. It made boot unstable due to the fact that PMIC at the start generates insufficient voltage for operation. See also: commit f4f57c58b589 ("rockchip: rk3188: Setup the armclk in spl"). Fixes commit 84a6a27ae3ff ("rockchip: rk3188: init CPU freq in clock driver"). Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-29clk: rk3399: Enable/Disable TCPHY clocksJagan Teki1-0/+24
Enable/Disable TCPHY clock for rk3399 platform. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-29clk: rk3399: Set empty for TCPHY assigned-clocksJagan Teki1-0/+2
Due to v5.7-rc1 sync the SD controller nodes in rk3399.dtsi have SCLK_UPHY0_TCPDCORE, SCLK_UPHY1_TCPDCORE assigned-clocks which are usually required for Linux and don't require to handle them in U-Boot. assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>; assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>; So, mark them as empty in clock otherwise device probe on those typec phy driver would fail. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-29clk: rk3399: Enable/Disable the USB2PHY clkJagan Teki1-0/+12
Enable/Disable the USB2PHY clk for rk3399. CLK is clear in enable and set in disable functionality. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-29clk: rk3399: Fix eMMC get_clk reg offsetJagan Teki1-1/+1
Actual eMMC get_clk register is clksel_con22 instead of clksel_con21. Fix it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-22clk: rk3399: Enable/Disable the PCIEPHY clkJagan Teki1-0/+6
Enable/Disable the PCIEPHY clk for rk3399. CLK is clear in both enable and disable functionality. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Suniel Mahesh <sunil@amarulasolutions.com> #roc-rk3399-pc Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-22clk: rk3399: Add enable/disable clksJagan Teki1-0/+148
Yes, most of the high speed peripheral clocks in rk3399 enabled by default. But it would be better to handle them via clk enable/disable API for handling proper reset conditions like 'usb reset' over command line. So, enable USB, GMAC clock via enable/disable ops. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Suniel Mahesh <sunil.m@amarulasolutions.com> # roc-rk3399-pc Tested-by: Suniel Mahesh <sunil@amarulasolutions.com> #roc-rk3399-pc Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-19common: Drop linux/bitops.h from common headerSimon Glass6-0/+6
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-19common: Drop linux/delay.h from common headerSimon Glass11-0/+11
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-19common: Drop linux/stringify.h from common headerSimon Glass6-0/+6
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-19common: Drop log.h from common headerSimon Glass12-0/+12
Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-01clk: rk3399: Set empty for HCLK_SD assigned-clocksJagan Teki1-0/+1
Due to v5.7-rc1 sync the SD controller nodes in rk3399.dtsi have HCLK_SD assigned-clocks which are usually required for Linux and don't require to handle them in U-Boot. assigned-clocks = <&cru HCLK_SD>; So, mark them as empty in clock otherwise device probe on those SD controllers would fail. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-04-02clk: rk3399: Set empty for vopl assigned-clocksJagan Teki1-0/+7
During vidconsole probe, the device probe will try to check whether the assigned clocks on that video console node is initialized or not? and return an error if not. But, unlike Linux U-Boot won't require to handle these vopl assigned-clocks since core clocks are enough to handle the video out to process. So, mark them as empty in set_rate to satisfy clk_set_defaults so-that probe happened properly. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Peter Robinson <pbrobinson@gmail.com>
2020-02-06dm: core: Create a new header file for 'compat' featuresSimon Glass11-0/+11
At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-06dm: core: Require users of devres to include the headerSimon Glass2-0/+2
At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
2020-01-30arm: rockchip: Add common cru.hJagan Teki2-39/+39
Few of the rockchip family SoC atleast rk3288, rk3399 are sharing some cru register bits so adding common code between these SoC families would require to include both cru include files that indeed resulting function declarations error. So, create a common cru include as cru.h then include the rk3399 arch cru include file and move the common cru register bit definitions into it. The rest of rockchip cru files will add it in future. Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-11-17rockchip: clk: Add clk driver for rk3308Finley Xiao2-0/+1073
Add clk controller driver for RK3308 SOC. This patch depends on Elaine's pll patch[0]. [0]http://patchwork.ozlabs.org/patch/1183718/ Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17rockchip: clk: pll: add common pll setting funcsElaine Zhang2-0/+361
Common PLL setup function, compatible with different SOC. Mainly for the subsequent new SOC use. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17rockchip: clk: fix wrong CONFIG_IS_ENABLED handlingHeiko Stuebner8-8/+8
CONFIG_IS_ENABLED() needs the config name like used in Kconfig, so without the leading CONFIG_. The clock drivers all wrongly check for CONFIG_RESET_ROCKCHIP, fix that Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17rockchip: clk: rv1108: remove duplicate reset initHeiko Stuebner1-14/+2
rockchip_reset_bind() already does the needed init for the reset registers, only referenced the wrong cru structure. So we can get rid of the open-coded reset init and just fix the correct cru reference. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17rockchip: clk: add px30 clock driverKever Yang2-0/+1631
The px30 contains 2 separate clock controllers, pmucru and cru. Add drivers for them. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-10clk: rockchip: rk3328: Configure CPU clockSimon South1-0/+2
Add a call to rk3328_configure_cpu() during initialization to set the CPU-clock frequency. Signed-off-by: Simon South <simon@simonsouth.net> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-09-11rockchip: clk: rk3399: remove clk_enable()Kever Yang1-37/+0
There is no real driver for clk enable/disable now, and we actually don't need it now, remove it so that not waste CPU cycles and code size. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-09-11rockchip: clk: rk3368: remove clk_enable()Kever Yang1-19/+0
There is no real driver for clk enable/disable now, and we actually don't need it now, remove it so that not waste CPU cycles and code size. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-09-11rockchip: clk: rk3328: remove clk_enable()Kever Yang1-12/+0
There is no real driver for clk enable/disable now, and we actually don't need it now, remove it so that not waste CPU cycles and code size. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-09-11rockchip: clk: rk3288: remove clk_enable()Kever Yang1-23/+0
There is no real driver for clk enable/disable now, and we actually don't need it now, remove it so that not waste CPU cycles and code size. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-08-23rockchip: clk: rk3328: add clk_enable ops for HCLK_HOST0Kever Yang1-0/+12
Required to successfully probe the ehci generic driver Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-29rockchip: rk3188: init CPU freq in clock driverKever Yang1-0/+3
Init CPU frquency in clock driver instead of in SPL board file, this will help for use common board file later. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-20clk: rockchip: rk3399: Set 400MHz ddr clockJagan Teki1-0/+4
Add support for setting 400MHz ddr clock. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-20clk: rockchip: rk3399: Set 50MHz ddr clockJagan Teki1-0/+4
Add support for setting 50MHz ddr clock. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19clk: rockchip: rk3399: Fix check patch warnings and checksJagan Teki1-37/+31
- CHECK: spaces preferred around that '*' - CHECK: spaces preferred around that '/' - CHECK: space preferred before that '|' - WARNING: macros should not use a trailing semicolon - CHECK: Unnecessary parentheses around 'fbdiv <= min_fbdiv' - CHECK: Unnecessary parentheses around 'parent->id == SCLK_MAC' - CHECK: Unnecessary parentheses around 'parent->dev == clk->dev' - WARNING: line over 80 characters - CHECK: Prefer kernel type 'u8' over 'uint8_t' - Add proper macro definitions arrangements Note: there are still line over 80 characters and other warnings but fixing those making code look unreadable, so I kept it as it is. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19rockchip: clk: rk3399: handle clk_enable requests for USB3Mark Kettenis1-0/+12
The "simple" OF glue layer for the Designware USB3 core enables all refernced clocks. These need to be need to be implemented otherwise the driver fails to probe. A dummy implementation that simply returns success is sufficient since the RK3399 comes out of reset with all clock gates open. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-30rockchip: clk: rk3399: allow requests for all UART clocksChristoph Muellner1-0/+2
This patch adds the rate for UART1 and UART3 the same way as already implemented for UART0 and UART2. This is required for boards, which have their console output on these UARTs. Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08rockchip: clk: rk322x: fix assert clock valueKever Yang1-2/+2
BUS_PCLK_HZ and BUS_HCLK_HZ are from BUS_ACLK_HZ, not from GPLL_HZ. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08rockchip: rk322x: add CLK_EMMC_SAMPLE clock supportKever Yang1-0/+2
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-01rockchip: use 'arch-rockchip' as header file pathKever Yang9-30/+30
Rockchip use 'arch-rockchip' instead of arch-$(SOC) as common header file path, so that we can get the correct path directly. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01rockchip: clk: Add mention of four new clocksSimon Glass1-0/+12
These clocks are needed to get MMC running. We don't actually support setting them yet. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01rockchip: rk3288: Add i2s pinctrl and clock supportSimon Glass1-0/+48
Add support for setting pinctrl and clock for I2S on rk3288. This allows the sound driver to operate. These settings were created by rkmux.py Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-11-30rockchip: rk3399: Initialize CPU B clock.Christoph Muellner1-9/+70
This patch sets the PLL of CPU cluster B (BPLL) to 600 MHz. This decreases the boot time of Linux 4.19 by about 8%. The 600 MHz are inspired by the 600 MHz used for LPLL initialization (came in with commit 9f636a249c1). Tested on RK3399-Q7 on Haikou base board. Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-11-30ARM: rockchip: rv1108: Sync clock with vendor treeOtavio Salvador1-6/+469
Make adjustments to the rv1108 clock driver in order to align it with the internal Rockchip version. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-10-28drivers: cosmetic: Convert SPDX license tags to Linux Kernel stylePatrick Delaunay1-2/+1
Complete in the drivers directory the work started with commit 83d290c56fab ("SPDX: Convert all of our single license tags to Linux Kernel style"). Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-05-14rockchip: clk: rk3288: handle clk_enable requests for GMACJonathan Gray1-0/+10
Since b0ba1e7e9d9b9441a18048ec67a3b3100c096975 (rockchip: clk: rk3288: add clk_enable function and support USB HOST0/HSIC) Ethernet no longer probes on RK3288. Add no-ops for GMAC clocks observed to be requested which match the clk_enable cases in RK3368 and RK3399. Signed-off-by: Jonathan Gray <jsg@jsg.id.au> Cc: Wadim Egorov <w.egorov@phytec.de> Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-05-07SPDX: Convert all of our single license tags to Linux Kernel styleTom Rini9-16/+9
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-04-27Remove unnecessary instances of DECLARE_GLOBAL_DATA_PTRTom Rini8-16/+0
We have a large number of places where while we historically referenced gd in the code we no longer do, as well as cases where the code added that line "just in case" during development and never dropped it. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-04-25rockchip: rv1108: add ofdata_to_platdata() method for driverKever Yang1-1/+9
Parse of data in dedicated api instead of in probe(). The clk_set_rate() may be called before the clk driver is probed, after core support set default clock. This patch fix system abort issue since: f4fcba5 clk: implement clk_set_defaults() Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-sytems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-sytems.com>
2018-04-25rockchip: rk3128: add ofdata_to_platdata() method for driverKever Yang1-1/+10
Parse of data in dedicated api instead of in probe(). The clk_set_rate() may be called before the clk driver is probed, after core support set default clock. This patch fix system abort issue since: f4fcba5 clk: implement clk_set_defaults() Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-sytems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-sytems.com>
2018-04-25rockchip: rk3036: add ofdata_to_platdata() method for driverKever Yang1-1/+10
Parse of data in dedicated api instead of in probe(). The clk_set_rate() may be called before the clk driver is probed, after core support set default clock. This patch fix system abort issue since: f4fcba5 clk: implement clk_set_defaults() Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-04-25rockchip: clk: rk3288: add clk_enable function and support USB HOST0/HSICWadim Egorov1-0/+13
The generic ehci-driver (ehci-generic.c) will try to enable the clocks listed in the DTSI. If this fails (e.g. due to clk_enable not being implemented in a driver and -ENOSYS being returned by the clk-uclass), the driver will bail our and print an error message. This implements a minimal clk_enable for the RK3288 and supports the clocks mandatory for the EHCI controllers; as these are enabled by default we simply return success. Signed-off-by: Wadim Egorov <w.egorov@phytec.de> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-03-29rockchip: clk: rk3188: update dpll settings to make EMAC workAlexander Kochetkov1-1/+1
The patch set dpll settings for 300MHz to values used by binary blob[1]. With new values dpll still generate 300MHz clock, but EMAC work. Probably with new values dpll generate more stable clock. dpll on rk3188 provide clocks to DDR and EMAC. With current dpll settings EMAC doesn't work on radxa rock. EMAC sends packets to network, but it doesn't receive anything. ifconfig shows a lot of framing errors. [1] https://github.com/linux-rockchip/u-boot-rockchip/blob/u-boot-rk3288/ tools/rk_tools/3188_LPDDR2_300MHz_DDR3_300MHz_20130830.bin Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
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