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path: root/drivers/clk/rockchip
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2023-08-12clk: rockchip: rk3308: Support reading UART rate and clock registersMassimo Pegorer1-0/+59
Add support to read RK3308 registers used to configure UART clocks, and thus to get UART rate and baudrate. This fixes clock_get_rate returning error on serial device probing. Moreover, there is no need anymore to use 'clock-frequency' property for UART nodes in *-u-boot.dtsi files for all cases where UART is not inited by U-Boot proper or by SPL o by TPL code but by a preliminary external boot phase (for Rock PI S, UART is inited by external TPL). Signed-off-by: Massimo Pegorer <massimo.pegorer+oss@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12clk: rockchip: rk3308: Fix ordering between masking and shiftingMassimo Pegorer1-5/+5
As per definitions of masks and shift offsets in cru_rk3308.h, values read from registers must be first masked and then shifted. By the way, this fix is binary invariant, because in all of fixed cases the shift offset is zero. Signed-off-by: Massimo Pegorer <massimo.pegorer+oss@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12clk: rockchip: rk3568: Add dummy support for GMAC speed clocksJonas Karlman1-0/+4
Pine64 Quartz64 boards DT reference SCLK_GMAC1_RGMII_SPEED in the assigned-clocks property of the gmac1 node. This result in a ENOENT error when driver core tries to set a parent for this clock. The clock speed in rgmii/rmii mode is changed using clk_set_rate of the tx_rx clock and not using clk_set_parent of the speed clock. Add dummy support for SCLK_GMAC1_RGMII_SPEED and similar clocks to clk driver to allow a driver for gmac node to probe. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12clk: rockchip: rk3568: Include UART clocks in SPLJonas Karlman1-3/+3
The clock driver for RK3568 does not include support for UART clocks in SPL. This result in the following message with high enough loglevel. ns16550_serial serial@fe660000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 Fix this by including support for UART clocks in SPL. Fixes: 4a262feba3a5 ("rockchip: rk3568: add clock driver") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Eugen Hristev <eugen.hristev@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12clk: rockchip: rk3568: Fix mask for clk_cpll_div_25m_divJonas Karlman1-1/+4
The field for clk_cpll_div_25m_div in CRU_CLKSEL_CON81 is 6 bits wide, not 5 bits wide as currently defined in CPLL_25M_DIV_MASK. Fix this and the assert so that CPLL_25M can be assigned a 25 MHz rate. Fixes: 4a262feba3a5 ("rockchip: rk3568: add clock driver") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-08-12clk: rockchip: rk3568: Fix clk selection in rk3568_pwm_get_clkDamon Ding1-1/+1
Fix use of wrong clk selection for CLK_PWM1 on RK3568. Fixes: 4a262feba3a5 ("rockchip: rk3568: add clock driver") Signed-off-by: Damon Ding <damon.ding@rock-chips.com> Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-31clk: rockchip: rk3328: Handle usb480m phy clockJagan Teki1-0/+2
Handle USB480M clock ID in set_rate() and set_parent() to allow the dt assigned-clocks and assigned-clock-parents work on rk3328.dtsi Cc: Lukasz Majewski <lukma@denx.de> Cc: Sean Anderson <seanga2@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-28rockchip: clk: clk_rk3568: Add CLK_PCIEPHY2_REF supportJonas Karlman1-0/+1
Add dummy support for the CLK_PCIEPHY2_REF clock. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-17reset: rockchip: implement rk3588 lookup tableEugen Hristev1-1/+1
The current DT bindings for the rk3588 clock use a different ID than the one that is supposed to be written to the hardware registers. Thus, we cannot use directly the id provided in the phandle, but rather use a lookup table to correctly setup the hardware. This approach has been implemented already in Linux, by commit : f1c506d152ff ("clk: rockchip: add clock controller for the RK3588") Hence, implement a similar approach using the lookup table, and adapt the existing reset driver to work with SoCs using lookup table. The file rst-rk3588.c has been copied as much as possible from Linux. Adapt the clk rk3588 driver as well to bind the reset driver with the lookup table. Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
2023-05-09clk: rockchip: rk3588: add hardcoded assigned clocks valuesEugen Hristev1-0/+22
The CRU is being probed with a default set of assigned clocks, which are not implemented in the driver at all. Hence, when clk_set_defaults is called, it fails with ENOENT. This would not be a problem, as the CRU still handles all the required clocks, and the assigned clocks are default configs which are preprogrammed or not required for Uboot operations. However, the rockchip reset driver is being bound by the same DT node as CRU, as the reset driver has no DT node. But, when probing the reset node, it will call again the clk_set_defaults for the CRU node, and failing because of missing those specific clocks in the rk3588 clock driver. To avoid this, simply implement a basic set/get that will just return success and the default corresponding rate for the required assigned clocks. As those clocks were not supported in Uboot, not required for Uboot operations, there is no need to do any different kind of initialization. Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-05-09clk: rockchip: correct trivial typo in debug messageEugen Hristev13-16/+16
s/faile/failed in debug message Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21clk: rockchip: rk3588: Add limited TMCLK_EMMC clock supportJonas Karlman1-0/+2
The device tree sdhci node reference the TMCLK_EMMC clock, add limited support this clock to rk3588 cru driver. Fixes probe of sdhci driver. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21clk: rockchip: rk3568: Add dummy I2S1_MCLKOUT_TX clock supportJonas Karlman1-0/+2
A RK3568 device tree pmic node can reference the I2S1_MCLKOUT_TX clock in assigned-clocks, add dummy support to set parent of this clock to the rk3568 cru driver. Fixes probe of pmic driver and missing regulators on affected boards, rk3568-evb and rk3568-rock-3a. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21rockchip: rk3588: Add support for sdmmc clocks in SPLJonas Karlman1-0/+125
Booting from sdmmc on RK3588 currently works because of a workaround in the device tree, clocks are reordered so that the driver use ciu-sample instead of ciu, and the BootRom initializes sdmmc clocks before SPL is loaded into DRAM. The sdmmc clocks are normally controlled by TF-A using SCMI. However, there is a need to control these clocks in SPL, before TF-A has started. This adds a rk3588_scru driver to control the sdmmc clocks in SPL before TF-A has started, using scru regs. It also adds a small glue driver to bind the scmi clock node to the rk3588_scru driver in SPL. Fixes: 7a474df74023 ("clk: rockchip: Add rk3588 clk support") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-04-21clk: rockchip: clk_rk3288: add PCLK_RKPWMJohan Jonker1-0/+1
The rk3288 pwm nodes synced from Linux make use of PCLK_RKPWM instead of PCLK_PWM. They have the same pclk_cpu parent, so add PCLK_RKPWM to rk3288_clk_get_rate(). Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> # chromebook-jerry Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-03-19clk: rockchip: rk3568: add stubs for CLK_PCIEPHY_REF clocksVasily Khoruzhick1-0/+3
Device tree contains assigned-clock-rates property for these, but default value will work just fine Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2023-03-19clk: rockchip: rk3588: Fix clk_aux16m in clock driverJonas Karlman1-2/+2
The rate and error value is not returned for aux16m clocks, fix this. Fixes: 7a474df74023 ("clk: rockchip: Add rk3588 clk support") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-03-19clk: rockchip: rk3568: Fix reset handlerPeter Geis1-0/+2
The reset handler for rk3568 is missing its private data. This leads to an abort when a reset is triggered. => reset resetting ... "Synchronous Abort" handler, esr 0x96000045 elr: 0000000000a2bc04 lr : 0000000000a2bbd4 (reloc) elr: 00000000eff9bc04 lr : 00000000eff9bbd4 x0 : 00000000fdd20000 x1 : 0000000014000001 x2 : 000000000000fdb9 x3 : 00000000edf77e88 x4 : 00000000edf50e78 x5 : 00000000edf77530 x6 : 000000000000001d x7 : 00000000edf8a1d0 x8 : 00000000ffffffd8 x9 : 0000000000000008 x10: 000000000000000d x11: 0000000000000006 x12: 000000000001869f x13: 0000000086c290c5 x14: 000000009118e878 x15: 0000000000000000 x16: 00000000eff9bbb8 x17: 0000000012f8c119 x18: 00000000edf50dc0 x19: 0000000000000000 x20: 0000000000000001 x21: 0000000000000000 x22: 00000000edf85900 x23: 0000000000000001 x24: 00000000effe8bbc x25: 0000000000000000 x26: 00000000edf85940 x27: 0000000000000000 x28: 0000000000000000 x29: 00000000edf3c8e0 Code: d65f03c0 d5033fbf b9400661 529d9502 (b8216802) Resetting CPU ... Add the missing dev_set_priv to the rk3568 clk driver to fix this. Fixes: 4a262feba3a5 ("rockchip: rk3568: add clock driver") Signed-off-by: Peter Geis <pgwipeout@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> # radxa-cm3 Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
2023-02-28clk: rockchip: rk3568: add more supported clk rates for sdmmc and emmcVasily Khoruzhick1-0/+3
SDHCI driver may attempt to set 26MHz clock, but clk_rk3568 will return error in this case. Apparently, SDHCI silently ignores the error and as a result eMMC initialization fails. Add 25 MHz and 26 MHz clk rates for sdmmc and emmc on rk3568 to fix that. Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28clk: rockchip: pll: Add pll_rk3588 type for rk3588Jagan Teki1-3/+264
Add RK3588 pll set and get rate clock support. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28clk: rockchip: Add rk3588 clk supportJagan Teki2-0/+1997
Add clock driver support for Rockchip RK3588 SoC. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16clk: rockchip: Add rv1126 clk supportJagan Teki2-0/+1890
Add clock driver support for Rockchip RV1126 SoC. Signed-off-by: Joseph Chen <chenjh@rock-chips.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-01-16rockchip: clk: add watchdog clock to px30_clk_enableQuentin Schulz1-0/+3
Add the PCLK_WDT_NS clock to px30_clk_enable so that the watchdog driver can probe since it wants to enable this clock. Cc: Quentin Schulz <foss+uboot@0leil.net> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-12-19rockchip: rk3128-cru: sync the clock dt-binding header from LinuxJohan Jonker1-4/+4
In order to update the DT for rk3128 sync the clock dt-binding header. This is the state as of v6.0 in Linux. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-10-21Merge tag 'u-boot-rockchip-20221020' of ↵Tom Rini1-1/+1
https://source.denx.de/u-boot/custodians/u-boot-rockchip - dts update and sync for rk356x, rk3288, rk3399 from Linux; - Add rk3399 EAIDK-610 board support; - Update for puma-rk3399 board; - some fix and typo fix in different drivers;
2022-10-19rockchip: clk: pll: Fix constant typoMichal Suchanek1-3/+3
Fixes: bbda2ed584 ("rockchip: clk: pll: add common pll setting funcs") Signed-off-by: Michal Suchanek <msuchanek@suse.de> Link: https://lore.kernel.org/r/20220928104129.13240-1-msuchanek@suse.de
2022-10-19arm: rockchip: rk3399: Program PLL clock for DDR at 50 MHz in documented rangeXavier Drudis Ferran1-1/+1
The original code set up the DDR clock to 48 MHz, not 50MHz as requested, and did it in a way that didn't satisfy the Application Notes in RK3399 TRM [1]. 2.9.2.B says: PLL frequency range requirement [...] FOUTVCO: 800MHz to 3.2GHz 2.9.2.A : PLL output frequency configuration [...] FOUTVCO = FREF / REFDIV * FBDIV FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2 FREF = 24 MHz The original code gives FOUTVCO: 24MHz/1 * 12 = 288MHz < 800MHz And the resulting FOUTPOSTDIV is 288MHz / 3 / 2 = 48MHz but the requested frequency was 50MHz Note: 2.7.2 Detail Register Description PMUCRU_PPLL_CON0 says fbdiv Feedback Divide Value Valid divider settings are: [16, 3200] in integer mode So .fbdiv = 12 wouldn't be right. But 2.9.2.C says: PLL setting consideration [...] The following settings are valid for FBDIV: DSMPD=1 (Integer Mode): 12,13,14,16-4095 (practical value is limited to 3200, 2400, or 1600 (FVCOMAX / FREFMIN)) [...] So .fbdiv = 12 would be right. In any case FOUTVCO is still wrong. I thank YouMin Chen for confirmation and explanation. Despite documentation, I don't seem to be able to reproduce a practical problem with the wrong FOUTVCO. When I initially found it I thought some problems with detecting the RAM capacity in my Rock Pi 4B could be related to it and my patch seemed to help. But since I'm no longer able to reproduce the issue, it works with or without this patch. And meanwhile a patch[2] by Lee Jones and YouMin Chen addresses this issue. Btw, shouldn't that be commited? So this patches solves no visible problem. Yet, to prevent future problems, I think it'd be best to stick to spec. An alternative to this patch could be {.refdiv = 1, .fbdiv = 75, .postdiv1 = 6, .postdiv2 = 6}; This would theoretically consume more power and yield less jitter, according to 2.9.2.C : PLL setting consideration [...] For lowest power operation, the minimum VCO and FREF frequencies should be used. For minimum jitter operation, the highest VCO and FREF frequencies should be used. [...] But I haven't tried it because I don't think it matters much. 50MHz for DDR is only shortly used by TPL at RAM init. Normal operation is at 800MHz. Maybe it's better to use less power until later when more complex software can control batteries or charging or whatever ? Cc: Simon Glass <sjg@chromium.org> Cc: Philipp Tomsich <philipp.tomsich@vrull.eu> Cc: Kever Yang <kever.yang@rock-chips.com> Cc: Lukasz Majewski <lukma@denx.de> Cc: Sean Anderson <seanga2@gmail.com> Link: [1] https://opensource.rock-chips.com/images/e/ee/Rockchip_RK3399TRM_V1.4_Part1-20170408.pdf Link: [2] https://patchwork.ozlabs.org/project/uboot/list/?series=305766 Signed-off-by: Xavier Drudis Ferran <xdrudis@tinet.cat> Tested-by: Michal Suchánek <msuchanek@suse.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-09-04clk: rockchip: rk3399: Fix Unknown clock 77 on mmc@fe310000Michal Suchanek1-23/+43
Adding some debug prints I can see: MMC: mmc@fe320000: Got clock clock-controller@ff760000 76 mmc@fe310000: Got clock clock-controller@ff760000 77 Unknown clock 77 rockchip_dwmmc_get_mmc_clk: err=-2 mmc@fe310000: 3, mmc@fe320000: 1, mmc@fe330000: 0 According to kernel code the SDIO clock is identical to SDMMC clock except for the con 16->15 change. Add support for the clock to avoid the error. Signed-off-by: Michal Suchanek <msuchanek@suse.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-04-18rockchip: rk3066: add clock driver for rk3066 socPaweł Jarosz2-0/+718
Add the clock driver for the rk3066 platform. Derived from the rk3288 and rk3188 driver it supports only a bare minimum to bring up the system to reduce the TPL size for: SDRAM clock configuration. The boot devices NAND, EMMC, SDMMC, SPI. A UART for the debug messages (fixed) at 115200n8. A SARADC for the recovery button. A TIMER for the delays (fixed). There's support for two possible frequencies, the safe 600MHz which will work with default pmic settings and will be set to get away from the 24MHz default and the maximum of 1.416Ghz, which boards can set if they were able to get pmic support for it. After the clock tree is set during the TPL probe there's no parent update support. In OF_REAL mode the drivers ns16550.c and dw-apb-timer.c obtain the (fixed) clk_get_rate from the clock driver instead of platdata. The rk3066 cru node has a number of assigned-clocks properties that call the .set_rate() function. Add them to the list so that they return a 0 instead of -ENOENT. Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com> Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-04-18rockchip: clk: add clocks to px30_clk_enableChris Morgan1-0/+3
Add the HCLK_OTG, HCLK_SFC, and SCLK_SFC clocks to px30_clk_enable. Without this change U-Boot reports an error of "Enable clock-controller@ff2b0000 failed" on boot when using the SFC or USB in U-Boot. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-10-15clk: rockchip: rk3568: update clksElaine Zhang1-2/+9
fix up ppll init freq. support tclk_emmc. add freq (26M) for mmc device. fix up the sfc clk rate unit error. Change in V2: remove change id. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-10-15rockchip: px30: add support for setting cpll clockChris Morgan1-0/+3
Starting with commit 92f1e9a4b31c ("clk: Detect failure to set defaults") the clk driver for the PX30 for the Odroid Go Advance would no longer probe correctly, because setting the cpll and gpu clocks are not supported with the clk_px30 U-Boot driver. This adds support for setting the cpll clock to the clk_px30 driver. Another patch will update the U-Boot specific device-tree to remove the GPU clock which is not used by U-Boot. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-09-30WS cleanup: remove trailing empty linesWolfgang Denk1-1/+0
Signed-off-by: Wolfgang Denk <wd@denx.de>
2021-09-25treewide: Try to avoid the preprocessor with OF_REALSimon Glass4-20/+22
Convert some of these occurences to C code, where it is easy to do. This should help encourage this approach to be used in new code. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-25treewide: Use OF_REAL instead of !OF_PLATDATASimon Glass4-5/+5
Now that we have a 'positive' Kconfig option, use this instead of the negative one, which is harder to understand. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-25treewide: Simply conditions with the new OF_REALSimon Glass5-7/+7
Use this new Kconfig to simplify the compilation conditions where appropriate. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-04mmc: Rename MMC_SUPPORT to MMCSimon Glass1-3/+3
Rename these options so that CONFIG_IS_ENABLED can be used with them. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> [trini: Fixup some incorrect renames] Signed-off-by: Tom Rini <trini@konsulko.com>
2021-08-12rockchip: px30: Support configure SFCJon Lin1-0/+32
Make px30 SFC clock configurable Signed-off-by: Jon Lin <jon.lin@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-06-18rockchip: rk3568: add clock driverElaine Zhang2-0/+2960
Add rk3568 clock driver and cru structure definition. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-06-17clk: Allow force setting clock defaults before relocationSean Anderson1-1/+1
Since 291da96b8e ("clk: Allow clock defaults to be set during re-reloc state for SPL only") it has been impossible to set clock defaults before relocation. This is annoying on boards without SPL, since there is no way to set clock defaults before U-Boot proper. In particular, the aisram rate must be changed before relocation on the K210, since U-Boot will hang if we try and change the rate while we are using aisram. To get around this, extend the stage parameter to allow force setting defaults, even if they would be otherwise postponed for later. A device tree property was decided against because of the concerns in the original commit thread about the overhead of repeatedly parsing the device tree. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-02-02common: Drop asm/global_data.h from common headerSimon Glass5-0/+5
Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
2021-01-05dm: Use access methods for dev/uclass private dataSimon Glass11-11/+20
Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
2020-12-14dm: treewide: Rename ofdata_to_platdata() to of_to_plat()Simon Glass11-26/+26
This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-14dm: treewide: Rename dev_get_platdata() to dev_get_plat()Simon Glass4-5/+5
Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-14dm: treewide: Rename 'platdata' variables to just 'plat'Simon Glass4-5/+5
We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13dm: treewide: Rename auto_alloc_size members to be shorterSimon Glass11-18/+18
This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-11-13rockchip: rk3399: Init clocks in U-Boot proper if SPL was not runAlper Nebi Yasak1-6/+16
It's possible to chainload U-Boot proper from the vendor firmware in rk3399 chromebooks, but the way the vendor firmware sets up clocks is somehow different than what U-Boot expects. This causes the display to stay devoid of content even though vidconsole claims to work (with patches in process of being upstreamed). This is meant to be a rk3399 version of commit d3cb46aa8c41 ("rockchip: Init clocks again when chain-loading") which can detect the discrepancy, but this patch instead checks whether SPL (and therefore the clock init) was run via the handoff functionality and runs the init if it was not. Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
2020-10-31Merge tag 'u-boot-rockchip-20201031' of ↵Tom Rini1-0/+20
https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - New PX30 board: Engicam PX30.Core; - Fix USB HID support for rock960; - Remove host endianness dependency for rockchip mkimage; - dts update for rk3288-tinker; - Enable console MUX for some ROCKPi boards; - Add config-based ddr selection for px30;
2020-10-30clk: rockchip: rk3399: implement getting wdt/alive clocksJack Mitchell1-0/+20
In order to correctly calculate the designware watchdog timeouts, the watchdog clock is required. Implement required clocks to facilitate this. Signed-off-by: Jack Mitchell <ml@embed.me.uk> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-10-14treewide: Fix wrong CONFIG_IS_ENABLED() handlingAlper Nebi Yasak1-1/+1
CONFIG_IS_ENABLED() takes the kconfig name without the CONFIG_ prefix, e.g. CONFIG_IS_ENABLED(CLK) for CONFIG_CLK. Some of these were being fixed every now and then, see: commit 71ba2cb0d678 ("board: stm32mp1: correct CONFIG_IS_ENABLED usage for LED") commit a5ada25e4213 ("rockchip: clk: fix wrong CONFIG_IS_ENABLED handling") commit 5daf6e56d36c ("common: console: Fix duplicated CONFIG in silent env callback") commit 48bfc31b6484 ("MIPS: bootm: Fix broken boot_env_legacy codepath") Fix all files found by `git grep "CONFIG_IS_ENABLED(CONFIG"` by running ':%s/CONFIG_IS_ENABLED(CONFIG_\(\w+\))/CONFIG_IS_ENABLED(\1)/g' in vim. Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.2.3 (git 2.39.0) at 2024-07-09 10:36:23 +0300